FinFET Gate Replacement and Source-Drain Epitaxy
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing complex three-dimensional transistors like FinFETs, requiring advanced processing techniques to achieve precise gate formation and source/drain structures for improved carrier mobility and device performance.
Innovation Solution
The method involves forming fin structures on a substrate, patterning gate dielectrics and dummy gates, recessing the fin, and replacing dummy gates with metal gate stacks, along with forming source/drain epitaxy structures and interlayer dielectrics, to create a semiconductor device with enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar transistors are used, then manufacturing process is simple, but functional density is limited
Solution Approach 1:
The patent transitions from planar (2D) transistors to FinFET (3D) transistors by creating a vertical fin structure that extends into the third dimension. This dimensional change allows the gate to wrap around the channel region, providing better electrostatic control and enabling higher functional density without proportionally increasing manufacturing complexity
2Productivity
If geometry size is decreased, then production efficiency increases, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the fin structure, depositing gate dielectric, creating dummy gates, performing recess operations, and replacing with metal gates. This segmentation allows each step to be optimized independently, maintaining precision requirements at manageable levels while achieving overall high production efficiency through standardized process modules
3Reliability
If three-dimensional transistor structures are implemented, then carrier mobility improves, but processing complexity increases
Solution Approach 1:
Dummy gates are formed early in the process before the fin recess operation. This preliminary action simplifies subsequent processing by providing a protective mask during recess formation and establishing the gate region boundaries early, thereby reducing overall processing complexity despite the three-dimensional structure
4Manufacturing precision
If fin recess is performed, then source/drain structure precision improves, but manufacturing steps increase
Solution Approach 1:
The fin recess operation is combined with the source/drain epitaxial growth process. The recess creates the precise geometry needed for optimal source/drain contact, while the epitaxial growth simultaneously forms the source/drain regions. This merging of operations achieves high precision without proportionally increasing the total number of discrete manufacturing steps
Data Source
AI summary
A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.