3D FinFET Memory Device Area Reduction
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Solution Overview
Problem
The existing trench-type transistor structure in dynamic random access memory (DRAM) limits further improvement in storage capacity and storage density due to its large occupied area, hindering integration and efficiency.
Innovation Solution
A novel memory device and forming method that includes forming active regions separated by trenches, with a third trench of narrower width than the first trench, bit line doped regions, a segmented metal gate, and a capacitor connected to the source region, optimizing the transistor structure to reduce area occupancy and enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a trench-type transistor structure is used to improve integration, then device complexity is reduced, but storage capacity and storage density cannot be further improved due to large occupied area
Solution Approach 1:
The patent transitions from a planar trench-type transistor structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change allows the transistor to utilize vertical space rather than only horizontal plane area, significantly reducing the occupied footprint while maintaining electrical performance and enabling higher storage density
2Length of moving object
If the line width of transistor structure is minimized, then area is reduced, but storage capacity cannot be further improved
Solution Approach 1:
By introducing vertical fins that extend upward from the substrate surface, the transistor structure utilizes the third dimension (height) to increase functional area. This allows storage capacity to scale with fin height rather than being constrained by planar line width minimization, enabling continued capacity improvement without further reducing lateral dimensions
3Reliability
If a segmented metal gate is formed by etching, then transistor control is improved, but device complexity increases
Solution Approach 1:
The metal gate is divided into multiple segments along the fin structure, with each gate segment corresponding to a specific fin or group of fins. This segmentation enables independent control of individual fins, improving transistor performance through better electrostatic control and allowing selective activation of fins based on circuit requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the storage capacity and storage density of DRAM by minimizing transistor area and improving electrical properties, allowing for more efficient memory integration.
Implementation Method 1
forming a bit line doped region in the semiconductor substrate on two sides of the third trench and at the bottom of the first trench through an ion implantation process
Data Source
AI summary
A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.