Epitaxial Gate Conductor for Compact JFET Fabrication
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Solution Overview
Problem
Current semiconductor device fabrication technologies face challenges in scaling down junction field effect transistors (JFETs) and other devices while maintaining electrical properties, particularly in achieving compactness and improved performance through dimensional and voltage reduction.
Innovation Solution
The method involves forming a junction field effect transistor (JFET) using an epitaxial growth process with a uniform doping concentration, where a replacement gate structure is formed on a semiconductor substrate, and a functional gate conductor is epitaxially grown within an opening to ensure direct contact with the substrate, allowing for the integration of JFETs and metal oxide semiconductor field effect transistors (MOSFETs) with minimal process step increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication technologies are used to scale down JFETs, then device dimensions are reduced, but electrical properties deteriorate
Solution Approach 1:
The patent changes the doping concentration parameter by using an epitaxial growth process that provides a uniform doping concentration throughout the gate structure. This uniform doping maintains the electrical properties of the device while enabling scaling to smaller dimensions, resolving the contradiction between reduced device dimensions and maintained electrical performance.
Solution Approach 2:
The patent replaces conventional mechanical deposition methods with an epitaxial growth process. This substitution enables precise control over doping concentration and crystal structure, allowing the gate structure to maintain its electrical properties even as device dimensions are reduced through scaling.
2Reliability
If replacement gate process is used to form functional gate conductor, then direct contact with substrate is achieved, but process complexity increases
Solution Approach 1:
The patent uses a replacement gate process where a temporary gate structure is formed first, followed by source and drain region formation. The functional gate conductor is then epitaxially grown in the opening after removing the replacement gate. This preliminary action sequence enables direct contact between the gate conductor and substrate while organizing the complex process into manageable steps.
3Reliability
If epitaxial growth process is used with uniform doping concentration, then electrical properties are improved, but manufacturing complexity increases
Solution Approach 1:
The epitaxial growth process used in this patent serves multiple functions simultaneously: it forms the gate structure, provides uniform doping concentration throughout the gate, and maintains crystal structure integrity. By consolidating these multiple functions into a single process step, the patent improves electrical properties while minimizing the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of compact, high-performance JFETs and MOSFETs with improved electrical properties, facilitating the integration of multiple device types on a single substrate while maintaining the integrity of the semiconductor substrate's crystal structure.
Implementation Method 1
A functional gate conductor is epitaxially formed within the opening in direct contact with the exposed portion of the substrate
Data Source
AI summary
A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).