TFT Memory Cells on Both Sides of Logic Layer
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Solution Overview
Problem
Conventional 1T-1C memory cells face challenges in advanced technology nodes due to access transistor leakage, capacitor scaling, and embedding capacitors in lower metal layers, which limit memory density and increase standby power.
Innovation Solution
Implementing thin-film transistors (TFTs) as access transistors in memory cells, allowing for lower leakage and enabling capacitors to be placed in upper metal layers, thereby increasing memory density and reducing footprint while maintaining data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 1T-1C memory cells are used with access transistors in advanced technology nodes, then memory capacity can be increased, but access transistor leakage increases and standby power increases
Solution Approach 1:
The patent changes the material parameters of the access transistor from conventional silicon-based transistors to thin-film transistors (TFTs) with different semiconductor materials (e.g., oxide semiconductors, III-V族 compounds). This parameter change results in significantly lower off-state leakage current while maintaining the same memory cell structure, thereby reducing standby power consumption without sacrificing memory capacity
Solution Approach 2:
The patent replicates the memory cell structure with TFT-based access transistors throughout the memory array, replacing conventional transistors systemically. This copying approach allows the low-leakage特性 of TFTs to be applied uniformly across all memory cells, achieving cumulative standby power reduction proportional to the memory array size
2Quantity of substance
If capacitors are embedded in lower metal layers to increase density, then memory density increases, but manufacturing complexity and leakage issues worsen
Solution Approach 1:
The patent moves the capacitor placement from lower metal layers (traditional 2D planar arrangement) to upper metal layers, effectively utilizing the vertical dimension of the device structure. This dimensional repositioning allows capacitors to be placed in regions with more manufacturing flexibility and better access, reducing the complexity of capacitor formation and interconnection while maintaining high memory density
Solution Approach 2:
Instead of embedding capacitors in lower metal layers as conventionally done, the patent inverts the placement strategy by positioning capacitors in upper metal layers. This inversion leverages the advantages of upper layer fabrication (better process control, easier via formation) while achieving the same or higher memory density through optimized vertical stacking
3Quantity of substance
If capacitor size is reduced to increase memory density, then memory density increases, but capacitor aspect ratio increases making fabrication difficult
Solution Approach 1:
By relocating capacitors to upper metal layers, the patent enables capacitors to be formed with more favorable aspect ratios. The upper layers provide greater horizontal space and better via access, allowing capacitors to be fabricated with smaller vertical dimensions relative to their horizontal footprint, thus maintaining manufacturing precision while achieving higher memory density
Solution Approach 2:
The patent changes the fabrication parameters of capacitors by utilizing upper metal layer materials and processes that enable lower aspect ratio structures. This may involve using different dielectric materials, conductor fills, or formation processes that are optimized for upper layer fabrication, thereby improving manufacturing precision while increasing memory density
Data Source
AI summary
Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.