VNW FET Flip-Flop Standard Cell Layout
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Solution Overview
Problem
There is a lack of effective layout structures for flipflop circuits using vertical nanowire field effect transistors (VNW FETs) that can reduce the area and prevent fabrication variations in semiconductor integrated circuit devices.
Innovation Solution
The proposed solution involves a standard cell layout for flipflop circuits utilizing VNW FETs, where transistors are connected to feedback nodes at their tops and gate electrodes are interconnected in a specific configuration to minimize signal and gate interconnects, reducing the overall area and enhancing fabrication precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar transistors are used in flipflop circuits, then the circuit area is larger, but if vertical nanowire FETs are used with optimized layout, then the area is reduced while maintaining functionality
Solution Approach 1:
The patent transitions from conventional planar transistor layouts to vertical nanowire FET structures, utilizing the third dimension (vertical orientation) to reduce the footprint of transistors in the standard cell. The nanowire channels extend vertically between top and bottom electrodes, allowing multiple transistors to be packed more densely in the planar area while maintaining electrical functionality.
Solution Approach 2:
The patent merges multiple interconnect functions into shared structures. Specifically, common bottom electrodes are shared among multiple nanowire FETs of the same conductivity type, and gate interconnects are routed to simultaneously control multiple transistors. This merging reduces the total number of separate interconnect structures needed, thereby reducing overall cell area.
2Area of stationary object
If transistors are connected to feedback nodes through multiple interconnects, then connection reliability is maintained, but the area increases and fabrication variations increase
Solution Approach 1:
The patent combines multiple transistor connections to the feedback node into a single unified interconnect structure. By routing a common feedback interconnect to collect signals from multiple nanowire FETs simultaneously, the design reduces the number of separate interconnect paths, thereby reducing area and minimizing the accumulation of fabrication variations that would occur with multiple separate connections.
Solution Approach 2:
The feedback node interconnect structure is designed to serve multiple functions: it collects feedback signals from multiple nanowire FETs, provides a common reference potential, and maintains electrical continuity across the latch unit. This multi-functional design reduces the need for dedicated separate interconnects for each function, reducing area and fabrication sensitivity.
3Area of stationary object
If gate electrodes are individually connected to each transistor, then control precision is maintained, but the number of interconnects increases and area expands
Solution Approach 1:
The patent merges gate control functions by routing common gate interconnects to simultaneously control multiple nanowire FETs. For example, a single gate interconnect structure is used to apply the same control signal to multiple transistors within the latch unit, reducing the total number of gate interconnects from one per transistor to one per group of transistors, thereby reducing area and interconnect complexity.
Solution Approach 2:
Gate interconnect structures are designed with multi-functionality, serving to control multiple transistors simultaneously while also providing mechanical support and electrical reference planes. This universal design approach reduces the overall interconnect structure complexity and area compared to individual dedicated gate interconnects for each transistor.
Data Source
AI summary
A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.