Cyclic Etching for Fin Height Uniformity
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Solution Overview
Problem
Existing semiconductor device fabrication methods face challenges in preventing excessive etching of the upper portion of fin structures during the etching of device isolation layers, leading to spatial variations in fin height and potential deterioration in transistor performance.
Innovation Solution
A method involving a cyclic etching process with two steps, where the first step forms a thicker surface polymer and the second step forms a thinner one, using a pulsed RF bias with varying duty ratios and etchant compositions, to control the etching rate and prevent excessive recessing of fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step etching process is used to remove the device isolation layer, then the etching process is simple and fast, but the upper portion of the fin structure is excessively etched leading to spatial variations in fin height
Solution Approach 1:
The etching process is divided into multiple sequential steps with different conditions. The first step uses a first etchant to etch the device isolation layer, while the second step uses a second etchant with different composition to reduce etching of the fin structure. This segmentation allows each step to be optimized for its specific function, achieving both high productivity and manufacturing precision.
Solution Approach 2:
The etching process changes parameters between steps, including etchant composition (C/F ratio), pressure, and RF bias power. These parameter changes enable control over the etching rate and selectivity, preventing excessive etching of the fin structure while maintaining efficient removal of the device isolation layer.
2Productivity
If the etching rate of the device isolation layer is increased to improve productivity, then the etching process is faster, but the fin structure is excessively recessed
Solution Approach 1:
The patent introduces an intermediary substance (surface polymer) that forms on the fin structure during etching. This polymer acts as a protective layer that reduces the etching rate of the fin structure while allowing the device isolation layer to be etched at a high rate. The polymer is subsequently removed in a cleaning step, leaving the fin structure protected from excessive recession.
3Manufacturing precision
If a high etch selectivity is maintained to protect the fin structure, then the fin height is preserved, but the etching process time is extended
Solution Approach 1:
The etching process uses periodic action by alternating between etching steps and cleaning steps. During etching steps, the device isolation layer is removed with high selectivity while the fin structure is protected by surface polymers. During cleaning steps, the surface polymers are removed and the process conditions are reset. This periodic action maintains high etch selectivity while limiting the total process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a large process window for etching the device isolation layer, reduces spatial variations in fin height, and maintains high etching selectivity, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
a pulsed RF bias power may be applied to a process chamber in which the first and second steps are performed
Implementation Method 2
an RF source may be configured to generate a pulsed RF bias power
Implementation Method 3
the first step may be performed to form a first surface polymer on a top surface of the fin structure, the second step may be performed to form a second surface polymer on the top surface of the fin structure
Implementation Method 4
an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step
Data Source
AI summary
A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.