Non-Uniform Gate Insulator for High Voltage Low Voltage Integration
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Solution Overview
Problem
The challenge lies in fabricating semiconductor devices that integrate high voltage and low voltage transistors on the same substrate while achieving optimal performance, as existing technologies face difficulties in balancing high breakdown voltage and current drivability due to the difference in voltage levels required for each type of transistor.
Innovation Solution
A semiconductor device with a gate insulating layer of non-uniform thickness is formed, comprising a thick first gate insulating layer on one portion and a thin second gate insulating layer on another portion, specifically for the P-type and N-type well regions, allowing for the formation of a lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) and complementary MOS (CMOS) devices, which enables simultaneous achievement of high breakdown voltage and current drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate oxide layer is used, then high breakdown voltage characteristic is obtained, but current drivability is lowered and on-resistance is increased
Solution Approach 1:
The patent applies local quality by forming a gate insulating layer with non-uniform thickness, where a first region has a greater thickness than a second region. This allows different portions of the gate insulating layer to serve different functions: the thicker first region provides high breakdown voltage for high voltage transistor components, while the thinner second region enables good current drivability for low voltage logic devices.
2Productivity
If a thin gate oxide layer is used, then current drivability is improved, but high breakdown voltage value is lowered
Solution Approach 1:
The patent applies local quality by forming a gate insulating layer with non-uniform thickness, where a first region has a greater thickness than a second region. This allows different portions of the gate insulating layer to serve different functions: the thicker first region provides high breakdown voltage for high voltage transistor components, while the thinner second region enables good current drivability for low voltage logic devices.
3Adaptability or versatility
If high voltage and low voltage transistors are simultaneously implemented on the same substrate, then integration is achieved, but fabrication difficulty increases due to voltage level differences
Solution Approach 1:
The patent applies local quality by forming a gate insulating layer with non-uniform thickness across different regions of the substrate. This enables simultaneous fabrication of high voltage and low voltage devices using a single process flow, where the thicker gate insulating layer regions support high voltage transistors and thinner regions support low voltage logic devices, thereby achieving integration without increasing fabrication complexity.
Data Source
AI summary
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.