CMOS Bias Generator for PVT-Stable Delay and Frequency Control
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Solution Overview
Problem
CMOS delay circuits are susceptible to process, voltage, and temperature (PVT) variations, leading to instability in time delay, which conventional voltage or current regulation techniques cannot effectively address due to long startup/settling times and requirement for closed-loop correction.
Innovation Solution
A novel bias generator using an operational amplifier and a resistive module, including a switched capacitor resistor, provides PVT-stable bias signals to CMOS delay circuits, ensuring the delay is independent of supply voltage and more accurately controlled, thereby achieving PVT stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage or current regulation techniques are used to control delay circuits, then the circuit can operate with simple biasing, but the time delay becomes unstable due to PVT variations and long startup/settling times
Solution Approach 1:
The bias generator pre-establishes stable bias conditions using an operational amplifier with resistive module and nMOS transistors configured to provide PVT-stable bias signals before the delay circuit operates, eliminating the need for long startup/settling periods associated with conventional regulation techniques
Solution Approach 2:
The patent introduces a specialized bias generator as an intermediary component between the power supply and the delay circuit. This bias generator uses an operational amplifier with a resistive module and nMOS transistors to mediate the bias signals, providing PVT stability without requiring closed-loop correction or long settling times
2Reliability
If conventional biasing methods are used, then the circuit design is simple, but the time delay is highly susceptible to PVT variations
Solution Approach 1:
The patent introduces a specialized bias generator as an intermediary component between the power supply and the delay circuit. This bias generator uses an operational amplifier with a resistive module and nMOS transistors to mediate the bias signals, providing PVT stability without requiring closed-loop correction or long settling times
Solution Approach 2:
The bias generator dynamically adjusts bias parameters (voltage and current) based on PVT conditions by using an operational amplifier with a resistive module and nMOS transistors configured to provide PVT-stable bias signals, allowing the delay circuit to maintain stable operation across process, voltage, and temperature variations
Data Source
AI summary
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.