Always-On CMOS Input Buffer for Low-Pin-Count Trim/Test Entry
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Solution Overview
Problem
Existing IC devices with low pin count or analog/no-connect pins face challenges in post-packaging trim and test operations, as conventional interfaces cannot access internal electrical nodes beyond those provided by packaging, leading to limitations in debugging and ensuring reliable operation, especially due to potential NVM charge loss during packaging.
Innovation Solution
A post-packaging trim/test interface architecture that includes a floating-pin-tolerant always-on CMOS input buffer, allowing for pin-only access and enabling quick debug access to test modes, which eliminates post-package shift in trim values and eliminates the need for wafer-level probing, by using a coupling capacitor and feedback path to manage slew rates and prevent through-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional trim/test interfaces are used in low pin count devices, then the device can be packaged with fewer pins, but post-packaging trim and test operations cannot access internal electrical nodes beyond those provided by packaging
Solution Approach 1:
The patent makes existing pins serve dual purposes: in normal mode they provide their designated functions, while in test mode they are reconfigured to provide access to internal electrical nodes that would otherwise be inaccessible. The pin assignment unit enables pins to be dynamically assigned to different functions including serving as test mode entry interfaces and providing access to internal nodes for trimming and testing operations.
Solution Approach 2:
The patent implements dynamic reconfiguration of pin functions based on operational mode. The pin assignment unit can dynamically assign pins to different roles including normal operation functions, test mode entry, and internal node access. This dynamic switching allows the same physical pins to provide different logical connections depending on whether the device is in normal mode or test mode.
2Device complexity
If analog or no-connect pins are used in normal mode, then the device achieves low pin count, but these pins cannot reliably serve as test mode entry interfaces due to floating pin issues
Solution Approach 1:
The patent introduces an always-on input buffer as an intermediary between the external pin and the test mode entry logic. This buffer remains active in both normal and test modes, providing a stable interface that eliminates floating pin issues. The buffer ensures that test mode entry signals are reliably detected even when the pin was originally designated for analog or no-connect functions in normal mode.
Solution Approach 2:
The patent prepares the always-on input buffer in advance to be ready for test mode entry at any time. The buffer is continuously active and pre-configured to detect test mode entry sequences, so when a test signal is applied to any pin including those designated as analog or no-connect pins in normal mode, the system can immediately recognize and respond to the test mode entry attempt without requiring pin reconfiguration or risking floating state issues.
3Ease of operation
If test mode entry is enabled on any pin, then debug access is improved, but false entry into test mode may occur due to through-current in input buffers
Solution Approach 1:
The patent implements feedback mechanisms where the always-on input buffer monitors incoming signals and provides feedback to the pin assignment unit and test mode entry logic. The system continuously monitors pin states and only transitions to test mode when the proper test mode entry sequence is detected, preventing false entry. The feedback ensures that normal operation signals do not accidentally trigger test mode while still allowing legitimate test mode entry sequences to be recognized.
4Measurement precision
If wafer-level probing is used for trim operations, then precise access to internal nodes is achieved, but the complexity and cost of the packaging process increases
Solution Approach 1:
The patent eliminates the need for wafer-level probing by making existing package pins serve multiple functions. The same pins that provide normal I/O functions also provide access to internal electrical nodes during test mode, achieving the precision of wafer-level probing without the added packaging complexity. The pin assignment unit enables these pins to be configured for internal node access when in test mode.
Solution Approach 2:
The patent extracts the test mode entry and internal node access functions from the wafer-level probing process and integrates them into the package pin interface. By moving these functions to the package level rather than requiring wafer-level access, the patent eliminates the need for complex wafer-level probing infrastructure while maintaining the ability to perform precise trimming and testing operations through the always-on input buffer and pin assignment unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides reliable and efficient trim and test capabilities, ensuring NVM reliability and quick debug turnaround times by preventing false entry into test mode and managing through-current, thus improving the operational stability of IC devices with limited pin counts.
Implementation Method 1
The always-on CMOS input buffer can, for example, include a coupling capacitor coupled at a first end to an input of the always-on CMOS input buffer and at a second end to a first end of a feed-forward path of the always-on CMOS input buffer
Data Source
AI summary
A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.