Fail-Safe Circuits TRIZ Cases
- Interrupter Circuit Diagnostics for Series Switch State Detection
A monitor signal injected between series switches enables independent state detection and fault signaling in safety interrupter circuits.
- FPGA Configuration Reload for Power Grid Fault Rectification
Automatic FPGA configuration reload corrects soft errors in power grid protection equipment with minimal downtime and no visible reboot.
- Output Pad Voltage Tracking for Multi-Voltage Fail-Safe I/O
Tracks gate and well voltages across 3.3V, 2.5V, and 1.8V domains to keep I/O pads fail-safe during power fluctuations.
- Failsafe Circuit Layout for Cross-Domain Signal Leakage Blocking
Dynamic gate control and pull-down switching enable cross-voltage signal transfer while blocking leakage when one power domain is off.
- Parity Reset Circuit for Partial Reset Attack Detection
Parity control and monitoring flip-flops detect partial reset anomalies and trigger a full reset to protect secure device operation.
- Always-On CMOS Input Buffer for Low-Pin-Count Trim/Test Entry
A floating-pin-tolerant CMOS buffer enables false-entry-free trim/test access on low-pin-count ICs while preventing through-current.
- Multi-Bit Scan Chain Parity Generation With Reduced Error Logic
Segmented multi-bit scan chains generate parity through shared flip-flops, cutting error-tree area and setup time in safety-critical cores.
- IO Failsafe Circuit for Ultra-Low PAD Leakage During Power Sequencing
A supply detector and failsafe circuit tri-state IO paths during power-up and power-down to prevent PAD leakage and conduction current.
- KNX Bus Output Protection Circuit for Short-Circuit Overheating
A protection circuit monitors KNX transmission output and instantly cuts resistor current during permanent short-circuits to prevent overheating.
- Programmable SoC Partitioning with NoC-Based Application Isolation
NoC-based partitioning lets programmable SoC subsystems run independently, improving resource sharing, reconfiguration, and data isolation.
- Floating-Pin-Tolerant Trim/Test Interface for Low-Pin ICs
A coupling-capacitor CMOS buffer enables false-entry-free trim and test access on low-pin ICs while blocking through-current and protecting NVM reliability.
- Programmable SoC Partitions With NoC Data Path Isolation
User-defined NoC data paths and isolated SoC partitions let multiple applications run concurrently while improving area and power efficiency.
- Memory Mode Register Test Circuit for Defect Detection
Built-in monitoring codes let memory write mode registers be checked for defects quickly, without complex external readout steps.
- Self-Isolating Output Driver for Powered-Down Bus Isolation
Isolation circuitry biases the PFET body and gate during power-down to block forward bias, unwanted current draw, and bus interference.
- FPGA Error Recovery Using Data Replay and Channel Reconfiguration
Parallel FPGA channels use error detection, data replay, self-test, and selective reconfiguration to correct reversible errors without service interruption.
- Scan Test Routing Circuit for Multi-Clock Domain ATPG
Selective scan-path routing and phased clock supply prevent timing errors across clock domains while keeping ATPG capture accurate.
- Programmable IC Platform With NoC Isolation for Multi-Tenant Acceleration
Programmable NoC paths and platform control let one IC share logic and processors across tenants while preserving isolation, power, and area efficiency.
- Combinatory Logic Fault Detection Using Bi-Residue Codes
Bi-residue modular arithmetic detects single event upsets in combinatory logic with lower area and energy overhead than redundancy.
- Wide-Voltage Output Interface Using De-MOS and Level Shifting
A level-shifted De-MOS output interface blocks reverse current and protects thin-oxide transistors across wide legacy supply voltages.
- Programmable NoC Platform for Flexible IC Function Remapping
A programmable NoC links logic and processors with user-defined data paths, improving IC flexibility, area use, and power efficiency.
- Multiturn Rotary Encoder Clock Monitoring for Pulse Failure Detection
A test clock and comparator detect missed measurement pulses in battery-powered multiturn encoders, preserving accurate revolution counts.
- Sectorized FPGA Architecture for Parallel Configuration Bandwidth
Local control in sectorized FPGA blocks enables parallel configuration, simpler support functions, and faster error correction.
- Dual-Sampling Logic Circuit for Transient Fault Detection
Delayed dual sampling compares two latch outputs to catch longer transient and timing faults without triggering false alarms.
- Flip-Flop Control Signal Integrity Checking Against Force Attacks
Feedback from each flip-flop verifies reset and scan control signals, detecting force-0 and force-1 attacks and triggering alarms.