Floating-Pin-Tolerant Trim/Test Interface for Low-Pin ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC devices with low pin count or analog/no-connect pins face challenges in post-packaging trim and test operations, as conventional interfaces cannot access internal electrical nodes beyond those provided by packaging, leading to limitations in debugging and ensuring reliable operation, particularly due to issues like NVM charge loss during packaging.
Innovation Solution
A post-packaging trim/test interface architecture that includes a floating-pin-tolerant always-on CMOS input buffer, allowing for pin-only access and enabling quick debug access to test modes, which eliminates post-package shift in trim values and reduces the need for wafer-level probing, by using a coupling capacitor and feedback path to manage slew rates and prevent through-current during normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trim/test interfaces are used in low pin count devices, then device functionality is maintained, but access to internal electrical nodes is limited and post-package shift occurs
Solution Approach 1:
The patent makes existing pins serve dual purposes: analog pins function as both analog inputs in normal mode and test mode entry interfaces when activated with specific clock patterns. This multi-functionality provides access to internal nodes without adding dedicated test pins, resolving the contradiction between maintaining simple device architecture and enabling comprehensive post-package testing and trimming capabilities
2Device complexity
If analog pins are used for test mode entry, then pin count is reduced, but false entry into test mode and through-current issues occur
Solution Approach 1:
The patent implements dynamic pin behavior where the same pin exhibits different characteristics based on operating conditions. During normal operation, the pin functions as an analog input with high impedance. When a specific number of clock cycles are detected, the pin dynamically transitions to digital mode enabling test mode entry. This dynamic switching resolves the contradiction by allowing pin reduction while preventing false test mode activation through context-dependent behavior
Solution Approach 2:
The system uses feedback mechanisms to detect the number of clock cycles applied to the analog pin and determines whether to transition to test mode. This feedback control ensures that test mode is only entered when the correct sequence is detected, preventing false entry while maintaining the ability to access internal nodes through the reduced pin count interface
3Manufacturing precision
If wafer-level probing is used for trimming, then manufacturing precision is improved, but productivity decreases and cost increases
Solution Approach 1:
The patent enables trimming operations to be performed after packaging by providing test mode access through the packaged device pins. This preliminary establishment of test access eliminates the need for post-package probing or wafer-level trimming, allowing trimming to be deferred to a later stage without compromising accuracy while significantly improving productivity by eliminating additional processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides reliable and efficient trim and test capabilities, ensuring NVM reliability and quick debug turnaround times by preventing false entry into test mode and managing through-current, thus improving the operational stability and accuracy of IC devices with limited pin counts.
Implementation Method 1
The always-on CMOS input buffer can, for example, include a coupling capacitor coupled at a first end to an input of the always-on CMOS input buffer and at a second end to a first end of a feed-forward path of the always-on CMOS input buffer
Implementation Method 2
The feedback path can include a feedback impedance. The always-on CMOS input buffer can further include a feedback path coupled at a first end to a second end of the feed-forward path of the always-on CMOS input buffer and at a second end to the second end of the coupling capacitor
Data Source
AI summary
A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.