Multi-Chip Logic Redundancy for Interconnect Yield Repair
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Solution Overview
Problem
The increased complexity in programmable logic devices, particularly in multi-die packages, leads to manufacturing defects and yield loss due to interconnect issues between dies, affecting device performance and functionality.
Innovation Solution
The implementation of a redundancy scheme that partitions integrated circuit dies into logic regions with spare regions, allowing for the identification and replacement of defective logic groups with spare logic groups and interconnects, ensuring continuous functionality by reconfiguring signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-die packages are assembled to increase functionality and integration, then device capability is improved, but manufacturing defects and yield loss increase due to interconnect issues between dies
Solution Approach 1:
The patent applies preliminary action by incorporating spare logic regions and interconnects into the multi-die package during manufacturing, before defects are detected. These spare resources are pre-configured and ready to be activated if defects are found during testing, thereby maintaining high manufacturing yield without compromising device capability.
Solution Approach 2:
The patent utilizes parameter changes by dynamically reconfiguring the logic regions and interconnects based on detected defects. Configuration parameters such as logic region activation states and interconnect routing are changed to bypass defective areas, allowing the device to maintain functionality despite manufacturing variations.
2Adaptability or versatility
If interconnects are added between logic regions on multi-chip packages to enable signal propagation, then device functionality is improved, but delay penalty increases due to signal propagation time
Solution Approach 1:
The patent employs intermediaries by introducing reconfigurable logic regions that can act as signal routing mediators. These logic regions provide alternative signal paths that can be dynamically selected to minimize propagation delay, effectively mediating between the functional requirements and timing constraints of the multi-die package.
3Reliability
If redundancy is implemented by adding spare logic regions and interconnects, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing spare logic regions and interconnects that can serve multiple functions. The same spare resources can replace different defective logic regions depending on where defects occur, and the reconfiguration mechanism can adapt to various defect patterns, reducing the overall complexity compared to having dedicated spare components for each possible defect location.
4Reliability
If logic groups are evaluated and reconfigured to replace defective groups with spare groups, then device reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the multi-die package into discrete logic groups that can be independently evaluated and reconfigured. This segmentation allows the manufacturing process to identify and repair defects at the logic group level rather than requiring complete package rework, simplifying the manufacturing process while maintaining high reliability.
Data Source
AI summary
A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.