Reset Detection Circuit Using Flip-Flop Pattern Verification
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Solution Overview
Problem
Existing digital electronic circuits face attacks where the reset signal is prevented from being asserted, leading to unintended features being enabled due to undetermined flip flop states upon power-up, resulting in a 50% chance of incorrect initialization.
Innovation Solution
A dedicated reset detection circuitry system that monitors the assertion of the reset signal and outputs a confirmatory signal, which can trigger a reset signal if the reset condition has not occurred, utilizing a group of flip flops configured to output a predetermined pattern and a comparator to verify the reset condition, ensuring proper initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset signal is prevented from being asserted (e.g., by lifting or overdriving the reset pin), then unauthorized features may be enabled due to undetermined flip flop states, but the system lacks a mechanism to detect or prevent this attack
Solution Approach 1:
The patent applies preliminary action by pre-configuring a group of flip-flops to output a predetermined pattern when properly reset, and pre-arranging a comparator to verify this pattern. This preparation occurs before the attack can take effect, enabling automatic detection of reset failures without adding complex external monitoring hardware.
Solution Approach 2:
The system performs self-service by using its own internal resources (flip-flops and comparator already present in the digital circuit) to detect reset conditions. The existing flip-flops are repurposed to generate a detection pattern, and the comparator uses this pattern to verify proper reset assertion, eliminating the need for separate dedicated detection hardware.
2Reliability
If a dedicated reset detection circuitry is implemented to monitor reset signal assertion, then correct initialization can be ensured, but the device complexity increases
Solution Approach 1:
The patent applies universality by making the flip-flops serve dual purposes: their primary function for normal circuit operation and a secondary function for reset detection. The same flip-flops that perform computational tasks also generate the predetermined pattern for verification, making the detection mechanism multi-functional rather than requiring dedicated single-purpose hardware.
Solution Approach 2:
The detection circuitry is merged with the existing digital circuit components. The comparator is integrated into the same logic structure, and the flip-flops are used both for their intended function and for generating detection signals. This merging eliminates the need for separate independent detection hardware, reducing overall device complexity.
3Manufacturing precision
If the flip flops are left in undetermined state without reset assertion, then the circuit may have 50% chance of incorrect initialization, but adding detection mechanism increases manufacturing complexity
Solution Approach 1:
The patent uses copying by creating a predetermined pattern in the flip-flops that serves as a reference copy of the expected reset state. The comparator then compares the actual flip-flop outputs against this predetermined pattern copy, enabling verification of correct initialization without requiring complex manufacturing processes or additional fabrication steps.
Data Source
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AI summary
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements are configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.