Four-Node Eight-Transistor Storage Cell for Soft Error Recovery
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Solution Overview
Problem
Six transistor SRAM cells and static flip-flops are vulnerable to soft errors due to low critical charge and increased sensitivity to radiation-induced transients, with existing solutions either being costly to implement or requiring more transistors, leading to higher power consumption and reduced frequency of operation.
Innovation Solution
An eight transistor storage cell topology that uses four n-channel and four p-channel transistors to interlock nodes against single-ended disturbances, providing robustness against soft errors while maintaining a smaller cell size and reduced leakage power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dual-inverter storage cell is used to store data, then the cell structure is simple and easy to implement, but the cell becomes vulnerable to soft errors due to low critical charge
Solution Approach 1:
The storage cell is segmented into four separate storage nodes (A, B, C, D) instead of the traditional two nodes. Each node is protected by dedicated transistors, creating four independent storage units that work together. This segmentation allows the cell to tolerate single-node upsets from soft errors while maintaining overall data integrity, directly addressing the vulnerability of simple dual-inverter structures to soft errors
Solution Approach 2:
The invention transitions from a two-node storage architecture to a four-node architecture, adding an extra dimension of redundancy. By distributing data across four nodes with cross-coupled feedback paths, the cell gains increased critical charge and soft error immunity without requiring a complete architectural overhaul, resolving the contradiction between simplicity and reliability
2Reliability
If more transistors are added to improve soft error robustness (e.g., DICE cell), then reliability improves, but the cell size increases and power consumption increases
Solution Approach 1:
The invention merges the storage functions of four nodes with cross-coupled feedback mechanisms into a unified eight-transistor structure. By combining the protective feedback paths and storage functions efficiently, the design achieves DICE-level soft error robustness in a more compact footprint, reducing the area overhead compared to traditional DICE cells while maintaining high reliability
Solution Approach 2:
Each transistor in the eight-transistor cell serves multiple functions: storage, feedback, and protection against soft errors. The cross-coupled transistors provide both data storage and error protection simultaneously, maximizing the functional utility of each transistor and reducing the overall cell size required to achieve high reliability
3Reliability
If more transistors are added to improve soft error robustness (e.g., DICE cell), then reliability improves, but leakage power consumption increases
Solution Approach 1:
The feedback mechanisms in the eight-transistor cell are designed to be dynamically active only when needed for error protection, rather than continuously consuming power. The cross-coupled transistors can enter low-power states when the stored data is stable, reducing leakage power while maintaining the ability to quickly respond to and correct soft errors when they occur
4Reliability
If critical charge is increased to improve soft error immunity, then reliability improves, but the cell size and transistor count increase
Solution Approach 1:
The invention changes the architectural parameters of the storage cell by introducing four nodes instead of two, which inherently increases the critical charge required for a soft error to occur. This parameter change achieves higher reliability through increased charge storage capacity while managing transistor count efficiently through shared feedback paths and multi-functional transistor design
Data Source
AI summary
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.