Scan Test Routing Circuit for Multi-Clock Domain ATPG
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Solution Overview
Problem
Automatic test pattern generation (ATPG) systems face challenges in testing circuits with multiple test paths belonging to different clock domains, leading to timing errors and incorrect test results due to the simultaneous application of shift clock signals.
Innovation Solution
The proposed solution involves a testing circuit with a routing circuit that selectively couples multiple test paths to a test access port circuit, allowing flexible setting of scan chain lengths and providing different clock signals to test paths in capture operation mode to avoid timing errors, while using the same clock signal in shift operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the same shift clock signal is provided to multiple test paths concurrently, then the testing process is simplified, but timing errors occur in test elements of different clock domains
Solution Approach 1:
The patent divides the clock signal provision into separate segments for different test paths. Each test path receives its own clock signal from dedicated clock supply circuits, allowing independent clock domain management. This segmentation prevents timing errors by ensuring that test paths in different clock domains receive appropriately synchronized clock signals rather than sharing a single clock signal.
Solution Approach 2:
The patent introduces clock supply circuits as intermediary components between the test clock pin and the test paths. These intermediary circuits process and distribute clock signals to different test paths, enabling proper synchronization for test paths in different clock domains while maintaining a unified testing interface.
2Device complexity
If test paths are fixed in configuration, then the circuit structure is simple, but the scan chain length cannot be flexibly adjusted to meet different testing requirements
Solution Approach 1:
The patent implements dynamic configurability in the test path connections through the routing circuit. The routing circuit can dynamically adjust and reconfigure which test paths are connected and how they are connected, allowing the scan chain length to be flexibly adjusted based on testing requirements while maintaining a relatively simple underlying circuit structure.
Solution Approach 2:
The routing circuit serves multiple functions: it can connect different test paths in series, parallel, or combinations thereof; it can adjust scan chain lengths; and it can adapt to different testing scenarios. This multi-functionality provides flexibility in scan chain configuration without requiring multiple dedicated circuit structures for each scenario.
3Device complexity
If multiple test paths are connected in a fixed series configuration, then the routing is simple, but the scan chain length becomes excessively long requiring extended test patterns
Solution Approach 1:
The routing circuit provides dynamic configuration options that allow optimization of scan chain length based on testing needs. Instead of a fixed series connection that always results in long scan chains, the routing circuit can adjust connections to create more balanced test path configurations, reducing the total scan chain length and corresponding test pattern requirements while maintaining routing simplicity.
Data Source
AI summary
A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.