Offset-Clock Error Detection in Digital IC Pipelines
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Solution Overview
Problem
Current fault-tolerance techniques in electronic systems, particularly integrated circuits, are costly and complex, and fail to effectively address transient errors caused by noise pulses without requiring complete duplication of systems, limiting their ability to adapt to varying levels of reliability and application-specific needs.
Innovation Solution
A flexible hardware mechanism that detects errors by using two clock signals offset in time, allowing for error detection and recovery without complete duplication, enabling varying levels of error detection granularity and control, and adapting to specific application requirements through a pipeline architecture with parity checks in registers and memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete duplication of systems is used for fault tolerance, then reliability is improved, but device complexity and cost increase significantly
Solution Approach 1:
The system is divided into two independent pipelines (first and second pipelines) that process the same instruction stream separately. Each pipeline operates independently with its own execution units, allowing fault detection through comparison while avoiding complete system duplication. The segmentation enables localized redundancy only where needed for error detection.
Solution Approach 2:
Instead of duplicating entire systems, the invention creates a simplified copy of the critical processing path. The second pipeline serves as a redundant copy that executes the same instructions simultaneously, and its results are compared with the first pipeline's results to detect errors without requiring full system duplication.
2Reliability
If traditional error detection methods are used, then reliability is improved, but area increase is significant
Solution Approach 1:
The error detection function is merged with the normal processing pipelines rather than being implemented as a separate dedicated circuit. The two pipelines themselves serve both computation and error detection purposes, with the comparison logic integrated into the existing structure. This combining approach achieves error detection without requiring additional dedicated error detection hardware area.
Solution Approach 2:
The pipelines are designed to serve multiple functions: normal computation and error detection. The same processing units that execute instructions also generate results for comparison-based error detection. This multi-functionality eliminates the need for separate error detection circuits, reducing the overall circuit area while maintaining reliability.
3Productivity
If clock speed is increased to maintain performance, then productivity is improved, but error detection capability deteriorates
Solution Approach 1:
The system uses periodic comparison of results from the two pipelines at specific intervals (after instruction execution) to detect errors. This periodic error checking mechanism allows the pipelines to operate at high clock speeds for most of the time while still maintaining error detection capability through regular comparison cycles, thus preserving both productivity and reliability.
Data Source
AI summary
Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.