Demultiplexer Circuit Using Series Replication for Defect Tolerance

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Solution Overview

Problem

As electronic circuits become increasingly smaller and more densely fabricated, manufacturing defects such as tiny specks of dust or misalignment during photolithography can lead to defective circuits, necessitating the development of defect-and-failure-tolerant methods without unnecessarily increasing complexity or costs.

Innovation Solution

The method employs series replication of transistors and error-control-coding-based signal-line redundancies in demultiplexers, using NMOS and PMOS transistors with serial and parallel redundancies to ensure functionality even with short or open defects, and incorporates error-control encoding techniques to introduce additional address-line-derived signal lines for enhanced defect tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant components are incorporated to achieve defect tolerance, then reliability is improved, but device complexity and manufacturing costs increase

Engineering Contradiction:

Improvedefect toleranceVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The demultiplexer is segmented into multiple functional blocks, each containing replicated transistor sets. Instead of replicating the entire demultiplexer, the circuit is divided into smaller units that can independently handle defects, reducing overall complexity while maintaining reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the structural parameters of the transistor interconnections by introducing series replication with specific numbering schemes (e.g., odd/even transistor arrangements). This parameter change enables defect tolerance through structural redundancy rather than functional redundancy, avoiding the need for complex control logic

Inventive Principle:

Principle #35Parameter changes

2Reliability

If redundant components are incorporated to achieve defect tolerance, then reliability is improved, but manufacturing costs increase

Engineering Contradiction:

Improvedefect toleranceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The invention uses copying of transistor structures within series chains rather than copying entire functional units. Multiple transistors are arranged in series with identical structural patterns, creating redundancy at minimal cost since the copied elements are simple transistor instances rather than complex subcircuits

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The invention applies partial redundancy by protecting only critical signal paths within the demultiplexer. Not all components are replicated, but only those necessary to tolerate the expected defect rate, achieving cost-effective reliability without excessive manufacturing overhead

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If series replication of transistors is used to tolerate short defects, then reliability is improved, but the number of transistors increases

Engineering Contradiction:

Improveshort-defect toleranceVSAvoidnumber of transistors

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The invention transitions from parallel redundancy (adding more transistors side-by-side) to series redundancy (arranging transistors in sequential chains). This dimensional change in the redundancy architecture allows defect tolerance through the series arrangement where a single functional path suffices, reducing the total transistor count compared to parallel approaches

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Reliability

If error-control encoding is used to tolerate open defects, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveopen-defect toleranceVSAvoidsignal-line complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention introduces intermediary signal lines that carry encoded versions of the address signals. These intermediary lines act as mediators between the original address inputs and the demultiplexer switching elements, providing error detection and correction capabilities through encoding schemes like parity bits or Hamming codes, thereby tolerating open defects without complex control logic

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7872502B2Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding

Publication Date: 2011.01.18 VALTRUS INNOVATIONS LTD

AI summary

One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.