Semiconductor Memory Refresh Control for Error Loop Prevention
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in continuously monitoring for errors and preventing refresh loops due to hard errors, which can lead to mismatched data and inefficient error rectification processes, especially when CPU priority is not high.
Innovation Solution
A semiconductor integrated circuit design featuring a majority circuit, error detector circuit, and monitor circuit that detects mismatches among storage elements, performs refresh actions, and notifies external units if rectification fails, thereby preventing refresh loops and enhancing reliability without relying on CPU operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous error monitoring and refresh actions are implemented, then reliability is improved, but device complexity increases due to additional monitor circuit and control logic
Solution Approach 1:
The patent combines the error detection function and refresh control function into an integrated monitor circuit. The monitor circuit simultaneously performs error detection on storage element outputs and generates control signals for refresh actions, merging multiple functions into a single circuit block to reduce overall device complexity while maintaining reliability improvements
Solution Approach 2:
The monitor circuit implements feedback by continuously monitoring error signals from the storage elements and automatically generating refresh control signals in response to detected errors. This closed-loop feedback mechanism enables automatic error rectification without external intervention, improving reliability while the feedback is handled within the integrated monitor circuit to limit complexity increases
2Reliability
If refresh actions are performed for all storage elements, then data integrity is improved, but loss of time occurs due to unnecessary refresh operations on error-free elements
Solution Approach 1:
The monitor circuit applies local quality by directing refresh actions only to specific storage elements that have been identified as containing errors. Instead of uniformly refreshing all storage elements, the circuit selectively applies refresh operations based on localized error detection, thereby maintaining data integrity for affected elements while avoiding time consumption on already correct elements
Solution Approach 2:
The patent implements partial action by performing refresh operations only on the subset of storage elements that require correction. The monitor circuit identifies erroneous storage elements through error signals and limits refresh actions to only those specific elements, rather than applying excessive refresh operations to the entire storage array, thus reducing time loss while maintaining data integrity
3Productivity
If CPU priority is set high for error handling, then productivity is improved through faster error rectification, but loss of time occurs when CPU priority is low causing refresh loops
Solution Approach 1:
The monitor circuit implements self-service by autonomously detecting errors and generating refresh control signals without requiring CPU intervention. The circuit independently manages the error rectification process, including identifying erroneous storage elements and initiating refresh actions, thereby eliminating dependency on CPU priority settings and preventing refresh loops caused by low-priority CPU handling
Solution Approach 2:
The patent applies preliminary action by having the monitor circuit detect and flag errors before they can cause system malfunction or require CPU intervention. The error detection and initial refresh control are prepared in advance by the monitor circuit, allowing immediate correction without waiting for CPU processing, thus improving productivity while avoiding the time loss associated with low-priority CPU handling
Data Source
AI summary
A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.