Eight-Transistor Storage Cell Topology for Soft Error Robustness
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Solution Overview
Problem
Six transistor SRAM cells and static flip-flops are vulnerable to soft errors due to low critical charge and increased sensitivity to radiation-induced transients, with existing solutions either being costly to implement or requiring more transistors, leading to higher power consumption and reduced frequency of operation.
Innovation Solution
An eight transistor storage cell topology with interconnected half-latches that stores data on four nodes, providing robustness against soft errors by interlocking transistors to prevent state changes from single node disturbances, while maintaining a smaller footprint and reduced leakage power compared to traditional dual-inverter storage cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual-inverter storage cell is used, then high speed and robust design are achieved, but soft error vulnerability increases
Solution Approach 1:
The storage cell is segmented into two separate latches (first latch and second latch) with distinct storage nodes (first node and second node), rather than using a single dual-inverter structure. This segmentation isolates the storage functions, preventing a soft error on one node from automatically propagating to the other node through feedback, thereby improving soft error robustness while maintaining operational speed.
Solution Approach 2:
Access transistors serve as intermediaries between the storage nodes and the external environment. These transistors control when storage nodes are connected to bitlines, preventing direct exposure of storage nodes to external disturbances. Additionally, the cross-coupled transistor structure acts as an intermediary that provides controlled feedback between latches, maintaining stability while reducing soft error propagation.
2Reliability
If more transistors are added to improve soft error robustness, then reliability improves, but cell area and leakage power increase
Solution Approach 1:
The first latch and second latch are merged into a single integrated storage cell structure with cross-coupled transistors. The access transistors are shared between both latches, and the storage nodes are cross-coupled through the transistor network. This merging achieves improved soft error robustness through the interlocked architecture while minimizing the increase in cell area compared to separate latch implementations.
3Ease of operation
If storage nodes are exposed to external signals, then data access is enabled, but sensitivity to radiation-induced transients increases
Solution Approach 1:
Access transistors serve as intermediaries that control the connection between storage nodes and external bitlines. During normal operation, these transistors enable data access by connecting storage nodes to bitlines. During radiation events, the transient nature of the disturbance is limited to the access transistor level and does not directly affect the storage nodes, as the intermediaries prevent direct exposure. This maintains ease of operation while reducing radiation sensitivity.
Data Source
AI summary
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.