Multi-Bit Scan Chain Parity Generation With Reduced Error Logic
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Solution Overview
Problem
Conventional circuit designs for safety-critical cores face inefficiencies in parity bit generation for error detection, requiring significant area and increased setup time due to extensive error tree logic, which is unacceptable for modern circuitry.
Innovation Solution
The implementation of a multi-bit scan chain architecture with an error-bit generator that optimizes area and performance by using a multi-bit flip-flop for parity-bit generation, incorporating mux-clock generator circuitry, scan chain circuitry, and error-bit generator circuitry to efficiently detect errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional parity bit generation logic is used, then error detection capability is achieved, but area consumption increases significantly due to extensive error tree logic
Solution Approach 1:
The patent segments the scan chain into multiple groups and generates parity bits for each group separately using dedicated flip-flops. This segmentation approach reduces the complexity and area of the error detection logic by dividing the large-scale error tree into smaller, manageable segments, each handled by its own parity generation unit.
Solution Approach 2:
The patent makes the scan chain flip-flops serve dual functions: they act as both data storage elements and parity generation units. By configuring certain scan chain flip-flops to generate parity bits for their respective groups, the design eliminates the need for separate dedicated parity generation logic, thereby reducing area consumption while maintaining error detection capability.
2Reliability
If conventional parity bit generation logic is used, then error detection capability is achieved, but setup time increases due to extensive error tree logic
Solution Approach 1:
By segmenting the scan chain into smaller groups with dedicated parity generation flip-flops, the patent reduces the depth and complexity of the error detection logic paths. This segmentation shortens the critical paths and reduces setup time requirements compared to a monolithic error tree structure that would process all bits through a single extensive logic network.
Solution Approach 2:
The patent performs parity bit generation in advance during the scan operation itself, using the scan chain flip-flops to compute parity bits as data moves through the chain. This preliminary action allows error detection to be prepared ahead of time, reducing the setup time burden on the main data path and allowing for more relaxed timing constraints.
3Area of stationary object
If multi-bit scan chain architecture with error-bit generator is used, then area efficiency is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent achieves area efficiency by making scan chain flip-flops multi-functional, serving both as data storage elements and as parity generation units. This approach reduces the need for separate dedicated parity logic circuits, thereby improving area efficiency without adding significant complexity beyond the reconfiguration of existing scan chain elements.
Solution Approach 2:
The scan chain architecture is designed to generate its own parity bits using its own flip-flops during the scan operation. This self-service approach eliminates the need for external or separate parity generation circuitry, reducing overall device complexity while maintaining area efficiency. The system uses its existing resources to perform error detection functions.
Data Source
AI summary
Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.