Memory Mode Register Test Circuit for Defect Detection
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Solution Overview
Problem
It is challenging to verify the normal operation of write mode register sets in semiconductor memory devices, as there is no method to read out the settings stored in these registers, making defect detection difficult and time-consuming.
Innovation Solution
A semiconductor memory device with a mode register circuit that includes write mode register sets and a defect detection circuit, where the write mode register sets store operational codes and output monitoring codes during a test mode, allowing the defect detection circuit to generate a defect determination signal based on these codes, thereby verifying defects in the write mode register sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write mode register sets are used to store operational codes, then the mode register circuit can function properly, but there is no method to read out the settings stored in these registers making defect detection difficult and time-consuming
Solution Approach 1:
The patent introduces an output control circuit as an intermediary component between the storing circuit and the external interface. This output control circuit enables selective output of stored codes by controlling the output enable signal, allowing read-out of write mode register settings without adding complex external testing equipment. The intermediary circuit resolves the contradiction by providing a built-in mechanism to verify defects while maintaining system functionality.
Solution Approach 2:
The patent changes the output state parameter of the write mode register sets by introducing a test mode signal that switches between normal operation mode and test mode. In test mode, the output control circuit enables reading of stored operational codes and monitoring codes, transforming the register sets from write-only to readable state. This parameter change allows defect detection without permanently altering the register structure or adding complex testing hardware.
2Productivity
If traditional testing methods are used for write mode register sets, then the device structure remains simple, but defect detection is difficult and time-consuming
Solution Approach 1:
The patent implements preliminary action by pre-configuring the output control circuit and defect detection circuit within the mode register circuit structure. These circuits are prepared in advance to automatically perform defect detection functions when test mode is activated, eliminating the need for time-consuming external testing procedures. The preliminary setup of reading and comparison circuits enables rapid defect identification, significantly improving testing efficiency while reducing testing time.
Solution Approach 2:
The mode register circuit performs self-service defect detection through the integrated output control circuit and defect detection circuit. The circuit automatically compares monitoring codes with expected values and generates defect determination signals without requiring external testing equipment or complex testing procedures. This self-service capability dramatically improves testing productivity while minimizing the time loss associated with traditional external testing methods.
Data Source
AI summary
According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.