Combinatory Logic Fault Detection Using Bi-Residue Codes
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Solution Overview
Problem
Current methods for mitigating Single Event Upsets (SEUs) in combinatorial logic are inefficient, as they require significant overhead in area, energy, and speed, and are not effective in determining which data is affected, especially in critical applications requiring real-time accuracy.
Innovation Solution
A system utilizing bi-residue codes, arithmetic compute logic, and comparators to detect and correct Single Event Effects (SEEs) by comparing outputs from multiple digital logic units operating with different moduli, allowing for efficient detection and correction of SEUs with reduced overhead and increased speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy based Radiation Hardening By Design (RHBD) methods are used to mitigate SEUs in combinatorial logic, then reliability is improved, but area requirements, energy requirements, and speed restrictions increase significantly
Solution Approach 1:
The patent changes the parameter space by operating in modular arithmetic domains (residue number systems) rather than standard binary arithmetic. By performing computations modulo different integers and using Chinese Remainder Theorem for reconstruction, the system achieves fault detection and correction with reduced hardware overhead compared to traditional redundancy methods
Solution Approach 2:
The patent replaces the mechanical redundancy approach (multiple identical circuit copies) with a mathematical substitution approach using residue codes and modular arithmetic. This substitution transforms the problem from a hardware replication task to a computational mathematics task, reducing area and energy requirements
2Reliability
If redundancy based Radiation Hardening By Design (RHBD) methods are used to mitigate SEUs in combinatorial logic, then reliability is improved, but energy requirements increase significantly
Solution Approach 1:
The patent changes the parameter space by operating in modular arithmetic domains (residue number systems) rather than standard binary arithmetic. By performing computations modulo different integers and using Chinese Remainder Theorem for reconstruction, the system achieves fault detection and correction with reduced hardware overhead compared to traditional redundancy methods
Solution Approach 2:
The patent replaces the mechanical redundancy approach (multiple identical circuit copies) with a mathematical substitution approach using residue codes and modular arithmetic. This substitution transforms the problem from a hardware replication task to a computational mathematics task, reducing area and energy requirements
3Reliability
If redundancy based Radiation Hardening By Design (RHBD) methods are used to mitigate SEUs in combinatorial logic, then reliability is improved, but speed restrictions increase significantly
Solution Approach 1:
The patent segments the arithmetic computation into independent modular operations. By dividing the computation into separate residue code generation stages and reconstruction stages, the system can process multiple data paths simultaneously without the speed penalties of sequential redundancy checking
Solution Approach 2:
The patent performs preliminary residue code generation on input operands before the main arithmetic operation. This preliminary encoding allows the main compute kernel to operate on already-protected data, and the reconstruction can occur in parallel, maintaining high speed while ensuring reliability
4Reliability
If conventional SEU mitigation methods are used, then reliability is improved, but the system cannot determine which data is affected
Solution Approach 1:
The patent implements feedback through the detector that compares results from different modulus computations. When discrepancies are detected, the feedback mechanism identifies which specific operand or result is affected by comparing against the expected residue relationships, providing error location information without requiring full redundancy
Data Source
AI summary
Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.