Dual-Sampling Logic Circuit for Transient Fault Detection
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Solution Overview
Problem
Modern integrated circuits are sensitive to transient perturbations and timing faults, and existing fault detection methods struggle to detect faults of large duration without producing false alarms, limiting the versatility of circuit designs.
Innovation Solution
The circuit incorporates a second sampling element with a delayed latching event and a comparator to analyze outputs from both sampling elements, allowing for a larger time interval between latching events, enabling detection of faults beyond the shortest circuit delay by adapting the clock signal's duty cycle and period, thereby increasing the duration of detectable faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the time interval between latching events is increased to detect faults of longer duration, then the duration of detectable faults is improved, but false alarms occur due to propagation delays
Solution Approach 1:
The circuit dynamically adapts its operation by supporting two modes: a first mode with a longer time interval for detecting longer faults, and a second mode with a shorter time interval to avoid false alarms. The system can switch between these modes based on operational requirements, making the fault detection mechanism flexible and adaptable to different timing scenarios.
Solution Approach 2:
The invention changes the timing parameters of the sampling elements by introducing a second time interval that is longer than the first. This parameter change allows the circuit to detect faults of longer duration while maintaining the ability to operate in a mode that prevents false alarms, thus resolving the contradiction between detection capability and reliability.
2Duration of action of moving object
If the clock period is increased to accommodate longer fault detection intervals, then the duration of detectable faults is improved, but the operating speed of the circuit is reduced
Solution Approach 1:
The circuit employs dynamic operation modes where it can switch between a first operating mode with a longer clock period for enhanced fault detection and a second operating mode with a shorter clock period for higher speed operation. This dynamic adaptability allows the system to optimize between detection capability and operating speed based on real-time requirements.
Solution Approach 2:
The invention utilizes periodic sampling events with different intervals - a first periodic interval for normal operation and a second, longer periodic interval for extended fault detection. By alternating between these periodic actions, the circuit can achieve both high-speed operation and long-duration fault detection without permanently sacrificing performance.
3Reliability
If dual sampling elements are added to detect faults, then the reliability of fault detection is improved, but the device complexity increases
Solution Approach 1:
The second sampling element serves multiple functions: it detects faults of longer duration, provides an alternative sampling point for comparison, and enables the circuit to operate in different timing modes. This multi-functionality justifies the added complexity by providing enhanced capabilities that a single sampling element cannot achieve.
Solution Approach 2:
The invention introduces a comparator as an intermediary element that analyzes the outputs of both sampling elements and generates error detection signals. This intermediary component simplifies the overall system by providing a clear decision mechanism that processes the data from multiple sampling points, making the complexity manageable and the fault detection systematic.
Data Source
Figure 1~2
Figure 3
Figure 4a~4b
AI summary
A circuit comprises a combinatory logic circuit having one input and one output (A). First and second sampling elements (92, 93) are connected to the output (A) and sample this output respectively at the activation of a first and second latching events determined by an event of first and second clock signals (CK). The event of second clock signal (CK) is delayed with respect to the event of a first clock by a delay which is shorter than the clock period. An analysis circuit (95) analyzes the outputs of the first and the second sampling elements and provides an error detection signal. The analysis circuit (95) sets the error detection signal (E) at the pre-determined value if the outputs of the first and second sampling elements (92, 93) are different. The circuit is used in a first operating mode in which the event of a second clock (CK) determining the second latching event is delayed with respect to the event of first clock (CK) determining the first latching event by a delay which is larger than a largest delay of the circuit.