Memory Error Correction Circuitry for Localized Soft Error Repair
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Solution Overview
Problem
Conventional error detection circuitry in programmable integrated circuits is limited in detecting and correcting soft errors, often resulting in incorrect error messages or failure to locate multiple errors, leading to unnecessary reconfiguration and power consumption.
Innovation Solution
The integration of error detection and correction circuitry with first and second data registers, a control circuit, and a comparator, which performs bit-wise comparisons using predetermined bit streams and error correction logic functions to detect and correct soft errors in configuration random-access-memory cells, allowing for selective correction of sensitive bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional error detection circuitry (e.g., CRC) is used to monitor CRAM cells, then error detection capability is provided, but the circuit can only detect and identify a limited number of soft errors (e.g., two errors), producing incorrect error messages or failing to locate three or more errors
Solution Approach 1:
The CRAM array is divided into multiple banks, with each bank monitored by dedicated error detection circuitry. This segmentation allows the system to independently track errors in each bank using bitwise XOR comparisons between current and previous state data, enabling accurate identification of multiple simultaneous errors across different banks that would overwhelm conventional single-array CRC methods
Solution Approach 2:
An error status register is introduced as an intermediary data structure to store and track the state of each CRAM bank. This register maintains bitwise XOR results between current and previous configurations, serving as a mediator that captures error information without requiring complex real-time analysis, thereby enabling reliable error location while maintaining detection accuracy
2Reliability
If the entire programmable device is reconfigured every time a soft error is detected, then reliable operation is restored, but unnecessary frequent disruptions and significant power consumption occur
Solution Approach 1:
Instead of globally reconfiguring the entire device, the system applies corrections locally to only those specific CRAM banks that contain detected errors. The error status register identifies which banks have errors, and reconfiguration is performed only on those localized banks, reducing power consumption and disruptions while maintaining overall system reliability
Solution Approach 2:
The system performs partial reconfiguration by updating only the necessary portions of the configuration memory (error-containing banks) rather than the entire device. This partial action is sufficient to restore reliability while avoiding the excessive power consumption and disruptions associated with full device reconfiguration
3Use of energy by moving object
If partial reconfiguration techniques are used to load configuration data into a portion of the device, then power consumption during reconfiguration is reduced, but error detection capability is not enhanced and errors may go undetected
Solution Approach 1:
The system performs preliminary error detection and tracking using the error status register before executing partial reconfiguration. By continuously monitoring CRAM bank states and storing error information in advance, the system ensures that errors are detected and recorded prior to any reconfiguration action, maintaining detection capability while enabling power-efficient partial updates
Data Source
AI summary
Integrated circuits with memory error detection and correction (EDC) circuitry are provided. The EDC circuitry may include first and second data registers and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with a predetermined bit stream. If a soft error is detected, correct bits generated using a logic function associated with the predetermined bit stream may be written back to the selected frame. In another suitable arrangement, the EDC circuitry may include first and second registers, a mask register, and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with desired data. The mask register may be loaded with mask bits. If a soft error is detected, the correct bits may be written back to the selected frame if the corresponding mask bits are high.