Interlocked Eight-Transistor Storage Cell for Soft Error Recovery

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Solution Overview

Problem

Six transistor SRAM cells and static flip-flops are vulnerable to soft errors due to low critical charge and increased sensitivity to radiation-induced transients, with existing solutions either being costly to implement or requiring more transistors, leading to higher power consumption and reduced frequency of operation.

Innovation Solution

An eight transistor storage cell topology that uses four n-channel and four p-channel transistors to interlock nodes against state changes, providing robustness against soft errors while maintaining smaller cell size and reduced leakage power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dual-inverter storage cell is used to store data, then the cell structure is simple and easy to manufacture, but the critical charge is low making it vulnerable to soft errors

Engineering Contradiction:

Improvesoft error robustnessVSAvoidcell structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The storage cell is divided into two separate latches (first latch and second latch) with distinct storage nodes (first storage node and second storage node). Each latch independently stores one bit of data, creating a segmented structure that increases critical charge and soft error robustness while maintaining manufacturing simplicity through modular design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Access transistors serve as intermediaries between the storage nodes and the external read/write circuits. These transistors control the coupling between storage nodes and bitlines, enabling soft error detection through differential reading while protecting the core storage structure from direct exposure to external signals that could induce soft errors

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If more transistors are added to increase critical charge (e.g., DICE cell), then soft error robustness improves, but cell area and leakage power increase

Engineering Contradiction:

Improvesoft error robustnessVSAvoidleakage power

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent uses exactly two latches with two storage nodes, which is the minimum configuration needed to achieve soft error detection capability. This partial action approach provides adequate soft error robustness without adding excessive transistors, thereby controlling leakage power and cell area while still achieving the desired reliability improvement

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The first latch and second latch are merged into a single integrated storage cell structure that shares common transistors and interconnect structures. This merging reduces the total transistor count compared to separate latches, decreasing leakage power and cell area while maintaining the soft error detection capability through the differential latch configuration

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If coupling capacitors are added to increase critical charge, then soft error robustness improves, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvesoft error robustnessVSAvoidmanufacturing process simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the mechanical/electrical coupling capacitor approach with a transistor-based latch structure. Instead of using capacitors to store and couple charge between storage nodes, the invention uses the inherent feedback mechanisms of CMOS latches, which are naturally compatible with standard CMOS manufacturing processes and do not require special capacitor fabrication steps

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If additional capacitance is added to increase critical charge, then soft error robustness improves, but write speed and operational frequency decrease

Engineering Contradiction:

Improvesoft error robustnessVSAvoidwrite speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The latch structure uses dynamic feedback through transistor gates to maintain stored data. The transistor switching action provides rapid charge transfer and state stabilization, enabling fast write operations. The dynamic nature of the transistor-based feedback mechanism allows for quicker response times compared to static capacitor-based charge coupling, maintaining high operational frequency while achieving soft error robustness

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8363455B2Eight transistor soft error robust storage cell

Publication Date: 2013.01.29 NYTELL SOFTWARE LLC

AI summary

A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.