FPGA Configuration Reload for Power Grid Fault Rectification
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Solution Overview
Problem
Existing electrical equipment in power grids is susceptible to soft errors caused by ionizing radiation and electromagnetic interference, leading to malfunctions and potential financial damage due to incorrect decision-making in protective devices, which current methods to identify and rectify faults are either complex, costly, or result in temporary failures and visible reboots.
Innovation Solution
An electrical equipment design with a preprocessing device featuring an integrated circuit and electronic memory chip that automatically identifies faults and interrupts operation until the logic circuit configuration is reloaded from a configuration memory chip, enabling rapid auto-refresh and reinitialization of the FPGA, reducing downtime to less than 30 milliseconds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automated identification of bit errors is carried out using checksum or CRC methods, then soft errors can be identified, but the identification process takes between a few milliseconds and one second which may lead to erroneous switching actions and damage
Solution Approach 1:
The patent applies preliminary action by continuously monitoring the FPGA configuration data in the configuration memory chip before errors can cause harmful effects. The system proactively detects bit flips as they occur rather than waiting for erroneous switching actions to manifest, enabling immediate rectification and preventing damage to the power grid equipment.
2Reliability
If redundant signal processing with three devices operated in parallel is used, then errors can be identified through 2 out of 3 evaluation, but the design becomes comparatively complex and expensive with increased space requirement
Solution Approach 1:
The patent uses copying by maintaining a configuration memory chip that stores a backup copy of the FPGA configuration data. This single copy serves as a reference for detecting bit flips in the active configuration, providing error detection capability without requiring multiple redundant processing devices. The configuration memory chip acts as a static backup that can be compared against the active configuration to identify errors.
3Reliability
If the FPGA performs a reboot to ensure reliable operation after an SEU, then correct operation is restored, but the protective device is not ready for approximately half a minute which constitutes a risk of consequential damage
Solution Approach 1:
The patent extracts the configuration data from the FPGA and stores it in a separate configuration memory chip. This separation allows the configuration to be monitored and rectified independently of the FPGA operation. When bit flips are detected, the configuration can be reloaded from the configuration memory chip without requiring a full system reboot, thus maintaining FPGA functionality while correcting configuration errors.
Solution Approach 2:
The patent applies discarding and recovering by detecting corrupted configuration data, discarding the erroneous bits through identification, and recovering the correct configuration by reloading from the configuration memory chip. This process restores correct operation much faster than a full reboot because only the configuration data needs to be refreshed, not the entire FPGA system.
4Reliability
If a reboot is performed to rectify soft errors, then reliable operation is restored, but the reboot is visible to customers and requires manual checking by engineers
Solution Approach 1:
The patent implements self-service by enabling the FPGA to automatically detect configuration errors and rectify them by reloading configuration data from the configuration memory chip without requiring manual intervention. The system monitors its own configuration integrity and performs self-correction, eliminating the need for engineer checking and avoiding visible disruptions to customers.
Data Source
AI summary
An item of electrical equipment has a preprocessing device for digital measured values. The preprocessing device has an integrated circuit and an electronic memory chip that contains a configuration of a logic circuit. If a fault of the preprocessing device is identified, an operation of the preprocessing device is interrupted until the configuration of the logic circuit has been loaded from a configuration memory chip into the electronic memory chip. There is also described a method for rectifying device faults, such as by reloading a configuration of a logic circuit into an electronic memory chip of a preprocessing device.