Programmable SoC Partitioning with NoC-Based Application Isolation
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Solution Overview
Problem
Modern programmable integrated circuits (ICs) face challenges in efficiently integrating heterogeneous subsystems, such as fixed-function components and programmable logic, to optimize area, power, and performance while maintaining flexibility and isolating applications across different partitions.
Innovation Solution
A System-on-Chip (SoC) platform with programmable logic circuitry, a processor system, and a network-on-chip (NoC) that allows user-defined data paths and is configured by a platform management controller, enabling common infrastructure sharing and dynamic reconfiguration of functions across subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous subsystems are integrated in modern programmable ICs, then functionality and performance are improved, but device complexity and area utilization become problematic
Solution Approach 1:
The device is divided into distinct heterogeneous subsystems including programmable logic circuitry, processor system, and network-on-chip, each with specialized functions. This segmentation allows independent optimization of each subsystem while maintaining overall system functionality through standardized interconnection interfaces.
Solution Approach 2:
The network-on-chip serves as a universal communication infrastructure that handles data transmission between different subsystems (programmable logic, processor, memory, I/O). This multi-functional interconnect reduces the need for dedicated point-to-point connections, thereby reducing device complexity while maintaining versatility.
2Productivity
If fixed-function components and programmable logic are combined, then performance is optimized, but area efficiency deteriorates
Solution Approach 1:
Fixed-function components (processor system, network-on-chip) and programmable logic circuitry are merged into a single integrated device architecture. This combination allows shared resources such as common memory structures, interconnect fabric, and clock distribution networks, improving area efficiency while maintaining the performance benefits of both fixed and programmable elements.
3Adaptability or versatility
If multiple subsystems are integrated, then functionality increases, but power consumption increases
Solution Approach 1:
The network-on-chip and interconnect structures are pre-configured during device initialization or idle periods, allowing the programmable logic and processor to access pre-established data paths. This preliminary setup reduces the need for dynamic reconfiguration during operation, thereby reducing power consumption while maintaining high functionality.
4Adaptability or versatility
If programmable logic and processor system are coupled, then flexibility is improved, but isolation between applications becomes difficult
Solution Approach 1:
Different regions or partitions of the programmable logic circuitry are assigned different security attributes and access permissions. The network-on-chip implements quality-of-service (QoS) policies that enforce isolation between applications by controlling data flow, resource allocation, and access rights at the local level, thereby maintaining flexibility while ensuring reliable application isolation.
Data Source
AI summary
A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.