CMOS Delay Bias Circuit Using Switched-Capacitor PVT Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS delay circuits are susceptible to process, voltage, and temperature (PVT) variations, leading to instability in time delay, which conventional voltage or current regulation techniques cannot effectively address due to long startup/settling times and require closed-loop correction.
Innovation Solution
A novel bias generator using an operational amplifier and a resistive module, including a switched capacitor resistor, provides PVT-stable bias signals to CMOS delay circuits, ensuring the delay is independent of supply voltage and more accurately controlled, thereby reducing PVT sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional voltage or current regulation techniques are used to control delay circuits, then the time delay can be adjusted, but the delay becomes susceptible to PVT variations and requires long startup/settling times or closed-loop correction
Solution Approach 1:
The patent changes the biasing parameters of the delay circuit by using a bias generator that produces PVT-stable bias signals. The bias generator includes an operational amplifier with a resistive module (switched capacitor resistor) that generates bias signals insensitive to PVT variations, thereby stabilizing the delay circuit's performance across process, voltage, and temperature changes without requiring closed-loop correction
Solution Approach 2:
The patent introduces a bias generator as an intermediary component between the power supply and the delay circuit. This bias generator acts as a mediator that converts unstable supply voltages into stable bias signals, isolating the delay circuit from PVT variations and eliminating the need for direct closed-loop control of the delay elements
2Reliability
If conventional biasing methods are used, then the circuit implementation is simple, but the time delay is not stable under PVT variations
Solution Approach 1:
The patent segments the delay circuit into two independent parts: a PVT-stable bias generation section and a delay element section. The bias generator is designed separately with specific PVT-insensitive components (switched capacitor resistor, operational amplifier), allowing it to be optimized for stability while the delay elements can be optimized for speed and area without compromising overall stability
3Measurement precision
If closed-loop correction is implemented to address PVT variations, then time delay precision can be maintained, but the system complexity and response time increase
Solution Approach 1:
The patent applies preliminary action by pre-stabilizing the bias signals before they reach the delay circuit. The bias generator is designed to inherently produce PVT-stable signals from the start, eliminating the need for subsequent closed-loop correction and reducing startup and settling times significantly
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a PVT-stable time delay by using PVT-stable bias signals, providing more precise control over the delay and reducing the impact of PVT variations, which is advantageous in semiconductor integrated circuits.
Implementation Method 1
the resistive module comprises a switched capacitor resistor having a switch, a first capacitor having a capacitance of CSW, and a second capacitor having a capacitance of CH
Data Source
AI summary
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.