CMOS Depth Sensor Element With Lightly Doped Region
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Solution Overview
Problem
Conventional CMOS depth sensor elements have slow transmission speeds of majority carriers, limiting their suitability for high-speed image sensors, especially in applications like Augmented Reality where quick non-contact input methods are essential.
Innovation Solution
A CMOS depth sensor element design featuring a substrate with a photosensitive region, semiconductor region, photogate, transfer gates, and lightly doped regions, where the photogate and transfer gates connect to a common lightly doped region with specific doping polarities, enhancing the movement speed of majority carriers through fringing electric field effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structure is used in depth sensor element, then device complexity is reduced, but transmission speed of majority carriers becomes slow
Solution Approach 1:
The semiconductor structure is segmented into multiple functional regions including a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. Each region serves specific functions for carrier generation, transfer, and readout, enabling faster majority carrier transmission while maintaining manageable structural complexity through functional specialization.
Solution Approach 2:
The patent implements a nested structure where the first and second transfer gates are formed within the first semiconductor region, the photogate is formed in the second semiconductor region, and floating diffusion regions are embedded within the third semiconductor region. This nested arrangement optimizes space utilization and enhances carrier transmission efficiency without proportionally increasing overall device complexity.
2Productivity
If conventional depth sensor element design is used, then manufacturing process is simplified, but sensing reaction rate becomes slow
Solution Approach 1:
The patent employs preliminary action by pre-positioning the first and second transfer gates in specific configurations within the first semiconductor region before carrier generation occurs. The photogate is pre-configured in the second semiconductor region with proper doping structures, enabling immediate and efficient carrier transfer upon light exposure, thus accelerating the sensing reaction rate while maintaining a systematic manufacturing process.
Solution Approach 2:
The patent implements dynamic control through the photogate and transfer gates that can be electrically controlled to modulate carrier flow. The gates can be dynamically switched to optimize carrier transfer timing and efficiency, enhancing the sensing reaction rate while using standard CMOS fabrication processes that maintain manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design accelerates the outputting speed of sensing signals by optimizing the movement of majority carriers, improving the linear performance and reaction speed of the depth sensor element.
Implementation Method 1
the depth of the majority carriers in the surface is effected by the lightly doped region when the driving signal is supplied. Then the linear performance that the majority carriers move in the photogate is also affected to achieve the purpose for increasing the moving speed of the majority carriers
Implementation Method 2
a substrate comprising a photosensitive region; a semiconductor region formed on the substrate; a photogate formed on the semiconductor region, corresponding to the photosensitive region
Data Source
AI summary
A complementary metal-oxide-semiconductor depth sensor element having a photogate formed in a photosensitive area on a substrate. A first transfer gate and a second transfer gate are formed respectively on two sides of the photogate in intervals. A first floating doped area and a second floating doped area are formed respectively on the outer sides of the first transfer gate and the second transfer gate. A semiconductor area is formed on the substrate. A lightly doped region is formed on the semiconductor area. The photogate, the first and second transfer gates and the first and second floating doped area are commonly formed on the lightly doped region. With the lightly doped region, the linear performance that the majority carriers move in the photogate is also affected to achieve the purpose for increasing the reaction rate.