CMOS Die Singulation via Trench Etching and Selective Layer Removal
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Solution Overview
Problem
Conventional methods for singulating integrated circuit die from wafers are inadequate for ultra-small and non-standard sizes and shapes, as they require minimum kerf spacing, lead to chipping, and are inefficient for large wafers with small die, resulting in wastage and high costs.
Innovation Solution
A method involving etching a semiconductor layer on a silicon oxide dielectric layer to form trenches, depositing a silicon nitride layer, filling with an oxide layer, and using selective wet or plasma etching to remove layers, allowing for the release of die from a carrier using solvents, enabling the separation of non-standard shaped die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If conventional sawing or scribe and crack methods are used for singulation, then the process is simple and straightforward, but the minimum kerf spacing requirement of 25 micrometers and chipping add 10 to 100 micrometers to the dimension, resulting in large wastage for ultra-small die
Solution Approach 1:
The singulation process is divided into multiple precise steps: etching trenches to define die boundaries, depositing silicon nitride layers in trenches, coating with oxide layers, and selective removal. This segmented approach allows for precise control of each step, achieving sub-micrometer precision and minimizing wafer wastage while enabling ultra-small die fabrication
Solution Approach 2:
Trenches are etched and filled with protective layers (silicon nitride and oxide) before the actual die separation. This preliminary action creates precise boundaries and protects against chipping during subsequent processing, enabling accurate die dimension control and reducing wastage
2Productivity
If conventional dicing technologies are used, then the process is straightforward, but it is limited to straight line cuts and requires more cuts for large wafers with small die, making dicing time prohibitive and costly
Solution Approach 1:
The etching process uses dynamic control to create both straight and curved trench patterns. The ability to switch between linear and curved etching paths allows for flexible die layouts (rectangular, circular, irregular shapes) while maintaining high productivity through automated process control
Solution Approach 2:
The process transitions from conventional 2D planar cutting to 3D trench formation and filling. By etching trenches and filling them with layered structures, the method enables complex 2D die patterns (including curved and irregular shapes) that cannot be achieved with simple straight-line sawing
3Reliability
If conventional mounting methods are used, then the process is simple, but ultra-small die tend to release prematurely, causing reliability issues
Solution Approach 1:
Silicon nitride and oxide layers are deposited in and around the trenches before die separation and mounting. These layers act as protective cushions that prevent chipping and provide mechanical support during handling, ensuring ultra-small die remain securely attached and preventing premature release
Solution Approach 2:
The silicon nitride and oxide layers serve as intermediary protective structures between the die and the external environment. These intermediate layers provide mechanical support and protection during mounting and handling, enhancing reliability without requiring complex mounting procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for rapid and cost-effective singulation of small or irregularly shaped die, reducing wastage and improving efficiency by enabling the use of existing semiconductor foundry practices.
Implementation Method 1
selective wet etching of the silicon nitride layer
Implementation Method 2
etching the oxide layer comprises etching by a technique of etching selected by from the group of techniques consisting of wet etching and plasma etching
Implementation Method 3
etching the oxide layer comprises etching by a technique of etching selected by from the group of techniques consisting of wet etching and plasma etching
Implementation Method 4
the releasing of the dies from the carrier comprises a solvent release
Data Source
AI summary
A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.