Solid-State Devices TRIZ Cases

A display device integrates touch electrodes and black matrix layers directly onto the encapsulation unit.

Coating process replaces thermal evaporation metal masks with hydrophobic bank layers, eliminating alignment complexity for large displays.

Surface plasmon coupling shifts the emission spectrum to achieve high efficiency and long lifespan without unstable blue phosphorescent materials.

An oxidation-resistant silicon nitride film protects the buried oxide layer in SOI substrates during thermal processing.

A laser-based LED transfer system moves light emitting diodes from a relay substrate to target substrates using precise alignment and robotic handling.

A segmented conductive layer design improves adhesion between connection members and array substrates.

Segmented doping regions balance high breakdown voltage against short reverse recovery time for reliable CMOS integration.

Structured ceramic conversion element directs primary radiation through microlens arrays to reduce inner total reflection and improve angular uniformity.

Replacing adhesive resin with a conductive bump eliminates protrusion defects while improving heat conduction efficiency.

Bending one end of the word line toward the select gate line creates space for contact plugs, avoiding short circuits and high resistance.

Alkali metal fluoride intermediate layer enhances electron injectivity in organic light-emitting devices.

Transparent light guiding poles transmit natural light to TFT sensors within a touching-type electronic paper cell.

Nitride and oxide spacer layers define source/drain stressor positions to ensure equal proximity for NFETs and PFETs, resolving uneven stress coupling.

A plane switch assigns CGN drivers to word lines, reducing chip area while maintaining control capability.

Selective removal of trench fill layers enables singulation of non-standard die shapes, reducing wafer wastage caused by conventional sawing kerf requirements.

Fluorinated polymers with electron-withdrawing groups replace acidic PEDOT:PSS to eliminate film deterioration and improve high-temperature durability.

A display panel incorporates alternating pixel units and transparent portions to transmit external light through the screen.

Stacked transparent conductive layers enable light emission through pixel circuit regions, increasing the opening ratio by over 21% for blue sub-pixels.

Insulation protection film prevents silver and aluminum diffusion into transparent conductive films, maintaining reflectivity and reliability.

Vertical gate stacking reduces lateral memory cell footprint, resolving integration density limits in non-volatile memory fabrication.

Segmenting the semiconductor body into distinct active regions enables precise UVA and UVB detection without increasing structural complexity.

Switch elements connect data lines during touch periods to eliminate separate array circuits and reduce manufacturing complexity.

Segmented support pillars use dielectric gaps to prevent electrical shorts, resolving reliability trade-offs in complex 3D memory fabrication.

Hard mask metal constrains contact hole dimensions to resolve manufacturing precision limits while protecting transistor stability.

A segmented common layer isolates driving current between adjacent organic light-emitting diodes to prevent unwanted light emission.

A Hall-effect sensor detects magnetic field variations from a saw-tooth ferrous target to generate position signals.

A variable resistance material forms a conductive filament to create a transparent electrode on micro LEDs.

An intermediate adhesion mediator resolves organic-inorganic interface conflicts while an ALD dielectric layer blocks moisture ingress.

Wafer bonding separates stacked vertical transistor formation into distinct substrate layers.

Vertical stacking of magnetoresistive bits resolves manufacturing precision limits at close spacings while maintaining electrical performance.

Nested encapsulating layers using silicon nitride or oxide reduce water vapor infiltration, enhancing reliability of wavelength conversion units.

A magnetic detection apparatus selects between AC and DC coupling modes to process signals from magnetoresistive elements.

Doping complementary color dyes into host layers produces candlelight emission, reducing eye discomfort from high color temperature white light.

Semicircular-columns in planarization and pixel defining layers distribute tensile stress to prevent metal wiring rupture during OLED display panel bending.

Merges imaging and inertial navigation sensors into a single integrated circuit package to eliminate bearing errors caused by separate mounting operations.

Segmented buffer layers isolate low temperature polysilicon and oxide semiconductor transistors, preventing manufacturing damage to pixel elements.

A dummy channel structure extends through stack layers to prevent bridge defects in vertical memory devices.

Vertical plugs link control electrodes to second wirings, simplifying manufacturing by avoiding wiring interference in the layout.

Vertical stacking of the switching and photo sensing transistors reduces horizontal area occupation, maintaining aperture ratio in in-cell displays.

A molecular memory device uses a cavity wider than conductive members to lengthen the current path.

Pivotable supporting arms lift cassettes through horizontal beams, reducing station height and preventing forklift collisions.

A TFT array substrate uses redundant scan lines to reduce active line count and improve opening ratio.

A resistance change memory uses a lightly-doped semiconductor layer in the word line to supply carriers and lower effective electrical resistance.

Parallel current leakage path with lower total resistance minimizes idle current leakage to prevent unintended dipole flipping and maintain non-volatility.

An auxiliary layer enables selective removal of organic material from non-display areas through thermal processing.

Asymmetric rectangular cross section reduces pixel cross talk and signal loss while maintaining high light reception efficiency.

Varying germanium concentration in SiGe zones via localized oxidation equalizes electron and hole mobility in CMOS transistors.

Optimized hole transport and electron control layer materials balance charge injection to reduce driving voltage and extend device lifespan.

Clamp devices connect substrate bias rails to supply nodes, reducing capacitive noise coupling and voltage variations that degrade device performance.