Ferroelectric Memory Cell Leakage Path Design
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Solution Overview
Problem
Ferroelectric memory cells with capacitors experience current leakage issues when idle, leading to unintended polarization changes and loss of non-volatility due to voltage differentials across the capacitor electrodes, which can erase programmed states over time.
Innovation Solution
Incorporating a parallel current leakage path with a lower total resistance than the intrinsic leakage path, configured to minimize current leakage during idle states and maintain electrode voltage equality, thereby reducing the electric field across the ferroelectric material and preventing dipole flipping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a select device is electrically coupled in series with a ferroelectric capacitor, then the memory cell can be addressed and controlled, but current leaks through the select device to adjacent substrate material when idle, causing voltage drop and creating voltage differential across capacitor electrodes
Solution Approach 1:
A parallel leakage path is introduced as an intermediary current route between the capacitor electrodes. This parallel path acts as a mediator that provides a controlled alternative for leakage current, preventing it from flowing through the select device and causing unwanted voltage drops. The parallel path effectively mediates the interaction between the select device leakage and the capacitor voltage stability.
Solution Approach 2:
The resistance of the parallel leakage path is specifically designed to be lower than the intrinsic leakage path through the ferroelectric material. By changing the resistance parameter of the parallel path, more leakage current is diverted through this controlled route, reducing the voltage differential across the capacitor electrodes and preventing unintended polarization changes.
2Reliability
If current leakage occurs through the select device when idle, then voltage differential is created between capacitor electrodes, but this erases programmed states of the memory cell over time, destroying non-volatility
Solution Approach 1:
The parallel leakage path is configured to preemptively counteract the harmful voltage differential that would otherwise develop across the capacitor electrodes. By providing a lower resistance path for leakage current before it can cause significant voltage drops, the system prevents the accumulation of electric field that would lead to dipole flipping and data loss, thereby preserving non-volatility.
3Loss of energy
If the intrinsic leakage path through ferroelectric material has high resistance, then less current leaks, but any leakage still creates sufficient electric field to flip dipoles and erase memory states
Solution Approach 1:
The parallel leakage path serves as an intermediary that intercepts and redirects leakage current away from the ferroelectric material. Even though the intrinsic leakage path has high resistance, the parallel path with lower resistance provides an alternative route that prevents the leakage current from creating damaging electric fields across the ferroelectric material, thus protecting memory state stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces unintended dipole changes and maintains non-volatility by ensuring negligible electric fields across the ferroelectric material, even when the memory cell is idle, thereby extending the retention of programmed states.
Implementation Method 1
Incorporating a parallel current leakage path with a lower total resistance than the intrinsic leakage path, configured to minimize current leakage during idle states
Implementation Method 2
Ferroelectric materials are characterized by having two stable polarized states. Polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and remains after removal of the programming voltage
Implementation Method 3
Even if small, such an electric field may start to flip individual dipoles in the ferroelectric material and continue until all are flipped, thus erasing a programmed state of the memory cell
Data Source
AI summary
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.