Vertical Memory Devices Dummy Channel Structure Bridge Defect Prevention
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Solution Overview
Problem
In vertical NAND flash memory devices, the high aspect ratio of channel holes leads to insufficient etching at the bottom of channel holes, resulting in not-open defects and incomplete exposure of the substrate in the block separation area, which causes bridge defects between neighboring gate lines.
Innovation Solution
A method is introduced where a dummy channel structure is arranged at the upper portion of the block separation trench, with a uniform vertical profile of the sidewalls, and the dummy channel structure is spaced apart from the substrate, allowing for sequential etching steps to form a block separation trench with small aspect ratios and preventing residual channels at the lower portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stack number of the stack layer structure is increased to increase memory capacitance and number of vertical memory cells, then the memory capacitance and number of vertical memory cells increase, but the aspect ratio of the channel hole becomes significantly increased causing insufficient etching around each bottom portion of the channel holes
Solution Approach 1:
The patent divides the single block separation area into multiple block separation areas by introducing dummy channel structures that extend to the substrate. This segmentation creates multiple separation zones that work together to prevent bridge defects while maintaining the high stack number configuration, thereby resolving the etching precision issue without reducing memory capacity.
Solution Approach 2:
The dummy channel structures act as intermediary elements between the channel holes and the substrate. These dummy structures extend through the stack layer structure to the substrate, providing intermediate separation zones that facilitate complete substrate exposure and prevent direct bridging between neighboring gate lines, thus solving the insufficient etching problem.
2Length of moving object
If the aspect ratio of the channel hole is high, then more vertical memory cells can be accommodated, but insufficient etching occurs around each bottom portion of the channel holes leading to not-open defects
Solution Approach 1:
The patent introduces dummy channel structures that extend through the stack layer structure to the substrate in advance, before the actual channel hole formation. These pre-positioned dummy structures create preliminary separation zones that ensure complete substrate exposure during etching, preventing not-open defects even with high aspect ratio channel holes.
Solution Approach 2:
The patent adds a new dimensional element by extending dummy channel structures vertically through the entire stack layer structure to the substrate. This vertical extension creates additional separation zones in the depth dimension, enabling complete substrate exposure and preventing bridge defects without compromising the horizontal spacing needed for high aspect ratio channel holes.
3Ease of manufacture
If the block separation area is covered by mask to form channel holes, then channel holes are formed in the cell block area, but the substrate cannot be sufficiently exposed in the block separation area due to insufficient etching
Solution Approach 1:
The patent applies different structural qualities to different areas: in the cell block area, standard channel holes are formed through the stack layer structure, while in the block separation area, dummy channel structures extend through to the substrate. This local differentiation ensures that the substrate is sufficiently exposed in the block separation area while maintaining ease of manufacture for channel hole formation in the cell block area.
Data Source
AI summary
Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.