CMOS Source/Drain Stressor Proximity Control

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Solution Overview

Problem

Conventional CMOS fabrication methods result in embedded source/drain stressors having different proximities to the channel for N-type and P-type field-effect transistors, leading to uneven stress coupling and performance enhancement, while scaling down gate lengths exacerbates short-channel effects and increases power consumption.

Innovation Solution

A method is developed to form CMOS structures with equal proximity of source/drain stressors to the channels of adjacent N-type and P-type field-effect transistors by using a stack of nitride and oxide layers to control the distance of stressors to the channel, ensuring consistent stress coupling for both types of transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional fabrication methods are used to form embedded source/drain stressors, then the stressors can be formed in NFETs and PFETs, but the proximity of the stressors to the channels becomes different, leading to uneven stress coupling and performance enhancement

Engineering Contradiction:

Improveease of forming embedded source/drain stressorsVSAvoiduniformity of stressor proximity to channel

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a sacrificial spacer layer before forming the source/drain stressors. This spacer layer is deposited and patterned to define the precise location where stressors will eventually be formed, ensuring both NFETs and PFETs receive stressors at identical distances from their respective channels. The spacer is then removed selectively, allowing subsequent stressor formation at the pre-determined uniform position.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses a sacrificial spacer layer as an intermediary element to mediate the positioning of source/drain stressors. This intermediary spacer is deposited over the gate regions, patterned to expose only the desired stressor formation areas, and then removed after defining the stressor locations. This intermediary structure enables precise control of stressor proximity without directly forming the stressors themselves, ensuring uniformity across different transistor types.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If gate length is scaled down to increase CMOS circuit speed, then circuit speed improves, but short-channel effects increase leading to higher off-state leakage currents and power consumption

Engineering Contradiction:

ImproveCMOS circuit speedVSAvoidshort-channel effects and off-state leakage

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by introducing embedded source/drain stressors with specific material compositions (SiC for NFETs providing tensile stress, SiGe for PFETs providing compressive stress) and controlled distances from the channel. These parameter changes in stressor material properties and positioning modify the stress state in the channel, which compensates for the detrimental effects of short-channel geometry, thereby reducing off-state leakage while maintaining high-speed operation.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If embedded source/drain stressors are formed closer to the channel, then stress coupling and carrier mobility enhancement improve, but the fabrication process becomes more difficult to control uniformly across NFETs and PFETs

Engineering Contradiction:

Improvecarrier mobility enhancementVSAvoidfabrication process control complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by using a single sacrificial spacer layer formation process that serves multiple functions: it defines the stressor formation location for both NFETs and PFETs simultaneously, ensures uniform spacing from channels for both transistor types, and provides a template for selective stressor deposition. This universal approach eliminates the need for separate positioning processes for different transistor types, simplifying fabrication control while achieving optimal stress coupling.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures consistent carrier mobility and performance enhancement for both N-type and P-type transistors, reducing short-channel effects and power consumption by maintaining equal stressor proximity, thereby improving overall CMOS circuit performance.

Implementation Method 1

using a stack of nitride and oxide layers to control the distance of stressors to the channel

Methodology Applied

Scientific EffectPhysical barrier:

Implementation Method 2

embedded SiGe (eSiGe) source/drain (SD) is used in PFETs for obtaining uniaxial compressive stress in the channel for mobility and performance enhancement

Methodology Applied

Scientific EffectStress coupling: Piezoresistive Effect

Data Source

PatentUS9059318B2Stressed source/drain CMOS and method of forming same

Publication Date: 2015.06.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal.