Resistance Change Memory With Lightly-Doped Word Line
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Solution Overview
Problem
Current resistance change type memory technologies face challenges in efficiently controlling the resistance state transitions and reducing power consumption, particularly in the write, erase, and read operations due to high current flow in unselected cells.
Innovation Solution
The implementation of a resistance change type memory design that incorporates a schottky junction between the word line and bit line via a resistance change film, utilizing a lightly-doped semiconductor layer in the word line, which reduces the effective electrical resistance by carrier supply from the bit line, thereby minimizing current consumption in unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional resistance change type memory structure is used, then the memory can perform basic read and write operations, but high current flows through unselected cells during write and erase operations, resulting in excessive power consumption
Solution Approach 1:
The memory structure is segmented into selected and unselected cell groups, with the lightly-doped semiconductor layer specifically positioned to control current in unselected cells. This segmentation allows differential resistance control where unselected cells maintain high resistance while selected cells can be programmed, directly reducing power consumption from unselected cell leakage
Solution Approach 2:
The word line is designed with non-uniform doping concentration, being lightly-doped in regions corresponding to unselected cells and having different doping in regions for selected cells. This local quality variation creates spatially-dependent resistance characteristics that minimize current flow in unselected cells while maintaining programming capability in selected cells
2Ease of operation
If the resistance of selected cells is lowered for programming, then write and erase operations can be performed, but the resistance of unselected cells also decreases, causing increased current leakage and power consumption
Solution Approach 1:
The lightly-doped semiconductor layer is positioned only in word line regions corresponding to unselected cells, creating local resistance differentiation. When programming voltages are applied, selected cells experience sufficient voltage to change resistance state while unselected cells with the lightly-doped layer maintain high resistance and suppress current leakage
Solution Approach 2:
The lightly-doped semiconductor layer acts as an intermediary element between the word line and unselected cells, mediating the voltage distribution to ensure that programming voltages do not cause excessive current flow in unselected cells. This intermediary structure enables selective programming while controlling leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient operation by lowering the resistance of selected cells while maintaining high resistance in unselected cells, thereby reducing power consumption and improving memory characteristics.
Implementation Method 1
utilizing a lightly-doped semiconductor layer in the word line, which reduces the effective electrical resistance by carrier supply from the bit line
Implementation Method 2
incorporates a schottky junction between the word line and bit line via a resistance change film
Data Source
AI summary
According to one embodiment, a resistance change type memory includes: a semiconductor substrate having a first impurity concentration; a first interconnect extending in a first direction perpendicular to a surface of the semiconductor substrate; a second interconnect including a first semiconductor layer, the first semiconductor layer extending in a second direction parallel to the surface of the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration; a memory layer between the first interconnect and the first semiconductor layer; a transistor including a second semiconductor layer between the first interconnect and the semiconductor substrate; and a third interconnect between the semiconductor substrate and the second semiconductor layer, and extending in the third direction.