Non-Volatile Memory Cell Fabrication Using Vertical Gate Stacking
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Solution Overview
Problem
The existing non-volatile memory devices with split-gate structures, such as SONOS devices, face challenges in increasing integration density and memory storage capacity due to larger memory cell sizes, which complicates the fabrication process and increases production costs.
Innovation Solution
A method of fabricating non-volatile memory cells involves forming second composite layers with charge storage layers between first memory cells, using a conductive layer to fill gaps and form second gates, and integrating gate structures without the need for additional photolithographic processes, allowing for higher density and simplified production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a split-gate structure is used in SONOS devices, then misjudgement errors due to over-erasure are prevented, but memory cell size increases and integration density decreases
Solution Approach 1:
The gate structure is segmented into control gates positioned at different heights - a first control gate above the charge storage layer and a second control gate above the first control gate. This segmentation allows the gates to be arranged vertically rather than horizontally, reducing the lateral footprint of each memory cell while maintaining the error prevention functionality of the split-gate structure
Solution Approach 2:
The patent transitions from a planar arrangement of control gates to a three-dimensional vertical stacking arrangement. By positioning control gates at different vertical levels (different z-dimensions) rather than side-by-side in the same plane, the invention reduces the lateral area occupied by each memory cell, thereby increasing integration density while preserving the reliability benefits of multiple control gates
2Reliability
If a split-gate structure with larger area is used, then charge storage and reading functions are improved, but the level of integration cannot be increased further
Solution Approach 1:
The invention resolves the integration density problem by moving the control gates into the vertical dimension. Multiple control gates are stacked at different heights above the charge storage layer, allowing them to perform their charge storage and reading functions effectively while occupying minimal lateral space. This vertical stacking enables higher integration levels without compromising the charge storage functionality
3Reliability
If additional select gates are formed on sidewalls and over substrate, then over-erasure errors are prevented, but fabrication complexity and production cost increase
Solution Approach 1:
The patent merges the formation of control gates with the existing memory cell fabrication process. The control gates are formed as integral parts of the memory structure during the same fabrication sequence, rather than requiring separate additional processing steps. This integration reduces fabrication complexity and production cost while maintaining the error prevention functionality
Solution Approach 2:
The control gates serve multiple functions simultaneously: they control charge storage in the underlying charge storage layer, enable reading operations, and prevent over-erasure errors. By designing the control gates to perform multiple functions within a single structural element, the invention reduces device complexity compared to having separate dedicated structures for each function
Data Source
AI summary
A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.