Stacked VTFET Integration via Wafer Bonding

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Solution Overview

Problem

Conventional approaches for forming stacked vertical transport field effect transistors (VTFETs) face challenges such as fin bending and undesirable loading effects due to the requirement for very tall fin formation, which limits transistor integration density.

Innovation Solution

The method involves forming vertical fin channels of stacked n-VTFETs and p-VTFETs sequentially, relaxing the RIE/fin height requirement and using wafer bonding post-bottom layer formation to simplify the process, allowing for higher transistor integration density by forming two layers of transistors separately on different Si layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If very tall fin formation is used to form stacked VTFETs, then vertical transport capability is improved, but fin bending and loading effects occur

Engineering Contradiction:

Improvefin heightVSAvoidfin bending and loading effects

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The stacked VTFET structure is divided into multiple separate fin channels (first fin channel, second fin channel, third fin channel) stacked vertically, with each fin having a controlled height. This segmentation allows achieving high vertical integration density without requiring excessively tall individual fins, thereby avoiding fin bending and loading effects while maintaining reliable vertical transport capability.

Inventive Principle:

Principle #1Segmentation

2Productivity

If conventional stacked VTFET formation is used, then vertical integration is achieved, but process complexity increases due to simultaneous formation requirements

Engineering Contradiction:

Improvetransistor integration densityVSAvoidprocess complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by separately forming different components on different substrates before stacking. Specifically, first and second VTFETs are formed on a first substrate, while a third VTFET is formed on a second substrate. This preliminary separate formation simplifies the overall process by avoiding complex simultaneous formation operations, reduces process steps, and enables higher transistor integration density through subsequent substrate stacking.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables much higher transistor integration density and simplifies the process of stacked transistors by relaxing the fin height requirements, reducing the likelihood of fin bending and other loading effects.

Implementation Method 1

bonding a second substrate to and on top of the first VTFET

Methodology Applied

Scientific EffectWafer bonding: Welding

Data Source

PatentUS11037905B2Formation of stacked vertical transport field effect transistors

Publication Date: 2021.06.15 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin and a second VTFET stacked on the first VTFET. The second VTFET includes a second semiconductor fin that is separate and distinct from the first semiconductor fin. At least one insulating layer is disposed on a top surface of the first VTFET. The second VTFET is disposed on the at least one insulating layer. The method includes forming a first vertical VTFET on a first substrate and bonding a second substrate to and on top of the first VTFET. A second VTFET is formed on the second substrate.