Microprocessor Substrate Bias Clamps for Noise Reduction
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Solution Overview
Problem
Conventional substrate bias rails in microprocessors experience significant impedance and capacitive noise coupling, leading to voltage variations and performance degradation, especially in large-scale devices like microprocessors where substrate bias voltages need to be distributed across the chip die.
Innovation Solution
The implementation of clamp devices and control logic to clamp substrate bias rails to core voltages, reducing noise and voltage variations by selectively turning on and off clamp devices based on operating modes, thereby minimizing sub-threshold leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If substrate bias rails are routed across the chip die to deliver bias voltages to distributed devices, then substrate biasing can be provided to reduce sub-threshold leakage current, but significant impedance and capacitive coupling cause voltage variations and noise that degrade device performance
Solution Approach 1:
The substrate bias distribution system is segmented into multiple local biasing regions, each with its own clamp device. Instead of relying on a single long bias rail, the die is divided into segments that can be independently biased, reducing the impedance and noise coupling along each segment while maintaining effective substrate biasing across the entire chip.
Solution Approach 2:
Clamp devices are introduced as intermediary elements between the substrate bias rails and the core voltage supply. These clamp devices act as mediators that actively regulate the substrate bias voltage, counteracting the effects of impedance and capacitive coupling by providing a stable reference point that reduces voltage variations and noise.
2Loss of energy
If bias generator raises bulk tie voltage above VDD and lowers below VSS during low power mode, then sub-threshold leakage current is significantly reduced, but voltage variations on substrates occur due to impedance of bias rail distribution
Solution Approach 1:
The clamp devices implement a feedback mechanism by continuously monitoring the substrate bias voltage and adjusting it to maintain a stable relationship with the core voltage. During low power mode, when the bias generator raises or lowers the bulk tie voltage, the clamp devices detect any deviations caused by impedance and provide corrective action, ensuring voltage stability while maintaining the low leakage current state.
Solution Approach 2:
The system dynamically changes the operating parameters of the substrate bias rails based on the operational mode. During low power mode, the bias generator modifies the bulk tie voltage parameters (raising above VDD or lowering below VSS), and the clamp devices adaptively adjust their clamping action to maintain appropriate voltage levels despite impedance effects, thereby preserving both power efficiency and voltage stability.
3Reliability
If multiple bias generators are provided on chip die to reduce voltage variations, then substrate biasing performance improves, but valuable die area is consumed
Solution Approach 1:
The clamp devices serve multiple functions: they act as voltage regulators during normal operation, provide noise filtering during low power mode, and serve as local reference points throughout the die. This multi-functionality allows a single clamp device to perform the work that would otherwise require multiple separate bias generators, reducing die area while maintaining voltage consistency.
Solution Approach 2:
The clamp devices are strategically positioned to serve their local regions autonomously, clamping the substrate bias voltage to the core voltage without requiring external intervention from a central bias generator. This self-service capability allows each clamp device to independently maintain voltage consistency in its local area, eliminating the need for multiple complex bias generator circuits across the die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces noise and voltage variations, improving device performance and power efficiency by maintaining consistent substrate bias voltages across the microprocessor die, even in low power modes.
Implementation Method 1
The bias voltage rails also introduce noise caused by capacitive coupling degrading device performance
Data Source
AI summary
A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.