SiGe Zone Ge Concentration Control for CMOS Carrier Mobility
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Solution Overview
Problem
Current microelectronic technologies face challenges in achieving equalized performance between N-type and P-type transistors in CMOS circuits, particularly due to the difficulty in enhancing the mobility of both electron and hole carriers using strained channels, and existing methods for producing semiconductor zones with different materials on a single substrate are complex and inefficient.
Innovation Solution
A method involving the formation of Si1-yGey semiconductor zones with varying Germanium contents on a substrate, where the Germanium content is adjusted through localized oxidation of Si1-xGex layers, using masks of varying thicknesses or compositions to create regions with different Germanium compositions, allowing for the fabrication of transistors optimized for electron and hole conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained channels are formed to improve carrier mobility, then the mobility of one type of carrier (electrons or holes) is improved, but the mobility of the other type of carrier deteriorates
Solution Approach 1:
The patent applies different strain conditions to different regions of the semiconductor structure. SiGe source/drain regions are formed with compressive strain to improve hole mobility in PMOS transistors, while SiN layers are deposited to induce tensile strain in specific regions for electron mobility enhancement in NMOS transistors. This localized application of different strain types allows each transistor type to benefit from optimized carrier mobility without compromising the other.
2Reliability
If different semiconductor materials are used for N-type and P-type transistor zones, then equalized performance can be achieved, but the fabrication process becomes complex with multiple intermediate steps
Solution Approach 1:
The patent merges the formation of SiGe source/drain regions and SiN strain layers into a single integrated fabrication process. The SiGe layers are deposited first, followed by oxidation to form SiGeO layers, then selective removal and SiN deposition in subsequent steps. This combined approach creates both the material differentiation needed for performance equalization and the strain structures for mobility enhancement within a unified process flow, avoiding the need for separate, complex fabrication sequences.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the SiGe source/drain regions and SiN strain layers before final transistor fabrication. The SiGe layers are deposited and oxidized in advance, creating a prepared substrate with pre-positioned strain structures. This preliminary preparation simplifies subsequent processing steps and allows for better process control and reproducibility.
3Productivity
If a single substrate is used for both N-type and P-type transistors, then device integration is achieved, but performance equalization becomes difficult
Solution Approach 1:
The patent implements local quality by creating spatially varying material compositions and strain conditions across the single substrate. SiGe source/drain regions are formed in specific locations with controlled Ge content, and SiN layers are deposited selectively to provide local tensile strain. This localized differentiation allows each transistor region to have optimized properties while maintaining overall device integration on a single substrate.
Solution Approach 2:
The patent utilizes parameter changes by varying the Ge content in SiGe layers and controlling the thickness and deposition conditions of SiN layers. These parameter variations create different strain magnitudes and material properties in different regions, enabling performance equalization between N-type and P-type transistors while maintaining substrate integration. The Ge concentration and SiN layer thickness are carefully controlled to achieve the desired balance in carrier mobility and transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of microelectronic devices with balanced performance between N-type and P-type transistors, reducing short channel effects and latching up issues while simplifying the fabrication process by creating semiconductor zones with tailored Germanium compositions on a single substrate.
Implementation Method 1
oxidation of the Si1-yGex based semi-conductor layer
Implementation Method 2
condensation of germanium
Data Source
AI summary
A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0<y<=1) that have different respective Germanium contents.