CMOS Duty Cycle Correction Loop Without Op-Amps
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Solution Overview
Problem
Current duty cycle correction circuits in integrated circuits face challenges such as transistor mismatch, operational amplifier requirements, and difficulty in maintaining precision over process, voltage, and temperature variations, which affect the accuracy and efficiency of clock signal duty cycle correction.
Innovation Solution
A CMOS duty cycle correction circuit utilizing a correction amplifier with a voltage-controlled resistor arrangement and a duty cycle detector forming a feedback loop, which includes an RC low pass circuit and a simple inverter cell, allowing for transistor mismatch cancellation and operational amplifier-free operation, enabling precise duty cycle correction across a wide frequency range with minimal chip area and low current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current mirrors are used to generate correction voltage, then duty cycle correction can be achieved, but transistor mismatch causes correction voltage offset
Solution Approach 1:
The patent removes the current mirror structure from the correction circuit, replacing it with a differential amplifier that directly compares the actual duty cycle voltage with a reference voltage. This extraction of the problematic current mirror eliminates the transistor mismatch issue while maintaining the correction function.
Solution Approach 2:
The patent introduces an intermediary reference voltage (Vref) that is carefully designed to be independent of transistor mismatches. This reference voltage acts as a stable mediator in the differential comparison, allowing accurate duty cycle measurement without being affected by transistor parameter variations.
2Measurement precision
If operational amplifiers are used for duty cycle correction, then correction functionality is achieved, but circuit complexity and chip area increase
Solution Approach 1:
The patent replaces expensive, complex operational amplifiers with simpler, more economical CMOS circuit elements including differential amplifiers, current mirrors, and RC circuits. This substitution achieves the same correction function with significantly reduced complexity and smaller chip area.
Solution Approach 2:
The correction circuit is segmented into distinct functional blocks: a duty cycle detection stage using RC circuits, a differential comparison stage, and a correction output stage. This segmentation allows each block to be optimized independently and simplifies the overall circuit design compared to using a monolithic operational amplifier.
3Measurement precision
If differential amplifiers compare actual DC voltage to reference voltage, then duty cycle detection is achieved, but zero offset of reference voltage is difficult to maintain over process, voltage and temperature variations
Solution Approach 1:
The patent makes the reference voltage dynamic rather than static, generating it through a controlled charging process that adapts to different duty cycle conditions. The reference voltage automatically adjusts its magnitude based on the input signal characteristics, maintaining accuracy across process, voltage, and temperature variations.
Solution Approach 2:
The patent changes the reference voltage parameter dynamically based on the detected duty cycle. By adjusting the reference voltage level according to the actual signal conditions, the system maintains accurate comparison without requiring a fixed zero-offset reference, thereby compensating for environmental variations.
4Measurement precision
If correction circuits use operational amplifiers and current mirrors, then duty cycle correction is achieved, but current consumption increases
Solution Approach 1:
The patent employs periodic sampling of the duty cycle using RC circuits that charge and discharge in synchronization with the clock signal period. This periodic action allows duty cycle detection without continuous high-current operation, significantly reducing average power consumption compared to operational amplifier-based continuous correction.
Solution Approach 2:
The patent uses simple RC circuits to create voltage copies proportional to the duty cycle rather than using power-hungry operational amplifiers. These voltage copies are sufficient for the correction function and consume minimal current, achieving the same effect with much lower power expenditure.
Data Source
AI summary
A CMOS integrated circuit (12) for correction of the duty cycle of a clock signal has a correction amplifier (16) to which a clock signal (14) is applied. The output of correction amplifier (16) is connected to an output buffer (18) and to an input of a duty cycle detector (20), the output of which is fed back to a control input (VC) of correction amplifier (16), thus forming a control loop. The duty cycle detector (20) comprises a buffer amplifier (22), an RC low pass circuit and a second inverter (24). A deviation of the duty cycle of the clock signal is detected in the duty cycle detector 20 and used to correct the duty cycle in the correction amplifier 16.