CMOS ECL I/O Circuit With Temperature-Tracked Signal Levels

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Solution Overview

Problem

Existing CMOS and ECL circuit technologies are not compatible due to differences in power supply and temperature sensitivity, making it difficult to interface CMOS circuits with ECL circuits without redesigning the entire system.

Innovation Solution

A CMOS ECL input/output circuit design that includes a CMOS differential amplifier with a temperature-dependent reference voltage, coupled with a feedback loop to maintain output signal levels similar to those of ECL circuits, allowing for seamless communication between CMOS and ECL circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If ECL circuitry is used to achieve high-speed operation, then the operating speed is improved, but the power consumption increases significantly

Engineering Contradiction:

Improveoperating speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent changes the fundamental operating parameters by using CMOS technology with different voltage levels and transistor characteristics compared to traditional ECL. The CMOS circuit operates at 5V or 3.3V power supplies with transistors that can fully turn on and off, unlike ECL's continuous current drawing bipolar transistors, thereby achieving high speed with reduced power consumption

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes bipolar transistor technology with CMOS technology, replacing the mechanical/electrical system of continuous current steering in ECL with the voltage-controlled switching mechanism of CMOS transistors, which achieve high-speed operation through voltage transitions rather than continuous current flow

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If bipolar transistor technology is used for ECL, then high-speed operation is achieved, but compatibility with CMOS circuits becomes difficult

Engineering Contradiction:

Improveoperating speedVSAvoidcompatibility with CMOS circuits

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent introduces an interface circuit as an intermediary between CMOS and ECL circuits. This interface circuit contains level shifters and buffer stages that translate between the voltage levels and signal characteristics of CMOS and ECL, enabling seamless communication between the two different technologies without requiring redesign of the entire system

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical parameters at the interface between CMOS and ECL circuits, including voltage level translation (from 5V/3.3V CMOS levels to ECL's negative voltage levels), impedance matching, and signal timing adjustment, thereby achieving compatibility while maintaining the high-speed capabilities of ECL

Inventive Principle:

Principle #35Parameter changes

3Speed

If ECL circuit design is used, then high-speed operation is achieved, but temperature sensitivity causes inherent shifting of input and output levels

Engineering Contradiction:

Improveoperating speedVSAvoidtemperature stability of voltage levels

Core Design Contradiction:

SpeedVSStability of the object's composition

Solution Approach 1:

The patent implements feedback mechanisms in the interface circuit that monitor and compensate for temperature-induced voltage level shifts. The feedback loop detects changes in ECL voltage levels due to temperature variations and adjusts the translation parameters accordingly, maintaining stable input and output levels across temperature ranges while preserving high-speed operation

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the use of CMOS processes in ASIC applications with ECL circuits, maintaining compatibility and operational speed while reducing power consumption by mimicking traditional ECL circuit behavior.

Implementation Method 1

The reference voltage varies based on a temperature of the CMOS ECL output circuit

Methodology Applied

Scientific EffectTemperature-dependent voltage reference:

Implementation Method 2

a feedback loop coupled between the output of the CMOS differential amplifier and the second input of the CMOS differential amplifier, and carries a signal to maintain the output signal of the ECL circuit at about the same level as the reference voltage

Methodology Applied

Scientific EffectFeedback: Feedback

Data Source

PatentUS7688110B2System for providing a complementary metal-oxide semiconductor (CMOS) emitter coupled logic (ECL) equivalent input/output (I/O) circuit

Publication Date: 2010.03.30 HONEYWELL INTERNATIONAL INC

AI summary

A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.