CMOS-to-ECL Converter Circuit for Low-Delay Differential Output
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Solution Overview
Problem
Conventional CMOS to ECL converters introduce significant delay, making them unsuitable for high-speed logic applications, as they require conversion of rail-to-rail CMOS signals to differential ECL signals with incompatible voltage levels.
Innovation Solution
A low-delay CMOS to ECL converter is designed using a reference level generator, a source follower, and an ECL buffer, which generates bias and reference signals based on CMOS supply voltage to convert CMOS input signals into differential ECL output signals, eliminating the need for a CMOS inverter and delay stage, and utilizing bipolar transistors to reduce conversion delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional CMOS to ECL converters are used, then signal conversion from rail-to-rail CMOS to differential ECL is achieved, but conversion delay is significant (400 pico seconds)
Solution Approach 1:
The patent extracts and eliminates the CMOS inverter and delay stage from the conventional converter architecture. By removing these components, the conversion delay is reduced from 400 pico seconds to 40 pico seconds while maintaining signal conversion accuracy through direct coupling of the CMOS input to the ECL differential pair.
Solution Approach 2:
The converter is segmented into distinct functional blocks: reference level generator, source follower stage, and ECL differential pair. This segmentation allows each component to be optimized independently, with the source follower providing voltage level translation and the differential pair providing differential output, achieving low delay without sacrificing conversion reliability.
2Adaptability or versatility
If CMOS supply voltage is used directly, then voltage level compatibility is achieved, but voltage level mismatch with ECL logic occurs
Solution Approach 1:
The source follower circuit acts as an intermediary between the CMOS rail-to-rail voltage and the ECL differential voltage levels. It translates the single-ended CMOS voltage into a form suitable for the ECL differential pair, ensuring both voltage level compatibility and logic level reliability without requiring additional level shifting stages.
3Speed
If bipolar transistors are used in ECL buffer, then conversion speed is improved, but device complexity increases
Solution Approach 1:
The patent merges the voltage translation function and differential signal generation into a single integrated stage using bipolar transistors. The ECL differential pair simultaneously performs voltage level adaptation and differential signal creation, achieving high conversion speed without proportionally increasing device complexity compared to multi-stage CMOS converters.
Data Source
AI summary
Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.