CMOS Floating Gate Resistive Processing Units for Cross-Bar Arrays
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Solution Overview
Problem
Current technologies for implementing machine learning computations in hardware using cross-bar arrays face challenges in efficiently representing and updating synaptic weight values, particularly due to the complexity of EEPROM fabrication and the need for efficient variable resistance mechanisms.
Innovation Solution
The use of complementary metal-oxide-semiconductor (CMOS) non-volatile analog memory elements with floating gates, where the resistance of resistive processing units is altered by controlling voltages applied between row and column wires, enabling efficient storage and updating of synaptic weight values in cross-bar arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EEPROM fabrication is used to implement cross-bar arrays, then non-volatile memory capability is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from EEPROM-based variable resistance mechanisms to a floating gate voltage-based control mechanism. By changing the fundamental operating parameter from resistance modulation to voltage-controlled charge storage, the system achieves non-volatile memory capability while being compatible with standard CMOS fabrication processes, thereby reducing manufacturing complexity
Solution Approach 2:
The patent replaces the complex EEPROM fabrication and variable resistance mechanism with a simpler floating gate voltage control system. The floating gate structure, formed using standard CMOS processes, substitutes for the more complex EEPROM architecture, achieving the same non-volatile function through electrical charge storage rather than resistance changes
2Adaptability or versatility
If variable resistance mechanisms are used in resistive processing units, then synaptic weight representation is enabled, but device complexity increases
Solution Approach 1:
The patent extracts the variable resistance function from the overall device structure and replaces it with a floating gate voltage control mechanism. By separating the weight storage function (floating gate charge) from the conduction path, the system achieves synaptic weight representation through voltage-controlled resistance modulation, simplifying the device structure while maintaining adaptability
Solution Approach 2:
The floating gate structure serves multiple functions simultaneously: it stores synaptic weight information through charge storage, controls the resistance of the resistive processing unit, and enables non-volatile memory capability. This multi-functionality reduces device complexity by eliminating the need for separate components for each function
3Productivity
If floating gate voltage control is used to adjust resistance, then synaptic weight update efficiency is improved, but measurement precision requirements increase
Solution Approach 1:
The patent implements feedback mechanisms through control circuits that read the floating gate voltage and adjust it accordingly to achieve desired synaptic weight values. The feedback loop enables precise control of the resistance by continuously monitoring and adjusting the floating gate voltage, thereby managing the measurement precision requirements while maintaining high update efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient hardware implementation of machine learning computations by enabling precise measurement and adjustment of synaptic weight values, enhancing the efficiency and adaptability of neural networks in cross-bar arrays.
Implementation Method 1
A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. A stored electrical charge of the floating gate provides a synaptic weight value of the resistive processing unit.
Implementation Method 2
The resistance of resistive processing units is altered by controlling voltages applied between row and column wires
Data Source
AI summary
A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.