CMOS Image Sensor Frontside Isolation for Smaller Pixel Crosstalk
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Solution Overview
Problem
Incorporating isolation structures and electrical circuits with CMOS image sensors becomes challenging due to increasing demand for higher image resolution and smaller pixel sizes, limiting the area for light detection and isolation, and disrupting molecular bonds during trench formation.
Innovation Solution
A multi-die CMOS image sensor with a frontside-based isolation structure using a dielectric layer that extends from the substrate's frontside to separate pixel cells, allowing better alignment and reducing pixel cell area, while forming the isolation structure early in the fabrication process to minimize defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation structures are incorporated between adjacent pixels to limit light escape and reduce crosstalk, then optical and electrical isolation between pixels is improved, but the available area for light detection in each pixel is reduced
Solution Approach 1:
The isolation structure extends vertically through the substrate thickness rather than only horizontally between pixels. By utilizing the depth dimension of the substrate, the isolation structure achieves effective optical and electrical separation without consuming lateral pixel area, thus resolving the contradiction between isolation effectiveness and light detection area.
Solution Approach 2:
The isolation structure is nested within the substrate volume by forming trenches that extend through the substrate thickness. This nested approach allows the isolation function to be embedded within the existing pixel structure without adding lateral footprint, maintaining maximum light detection area while achieving effective isolation.
2Measurement precision
If pixel size is reduced to increase image resolution, then the number of pixels per unit area increases, but the area available for both light detection and isolation structures becomes limited
Solution Approach 1:
By transitioning from two-dimensional lateral isolation to three-dimensional vertical isolation through substrate-thickness trenches, the design enables higher pixel density without compromising isolation effectiveness. The vertical dimension provides the isolation function, freeing up lateral space for increased pixel count and light detection area.
Solution Approach 2:
The substrate is segmented vertically into isolated regions through deep trenches that extend through the full substrate thickness. This segmentation approach allows individual pixels to be closely packed in the lateral direction while maintaining electrical and optical isolation through the vertical trench structures, enabling higher resolution without sacrificing isolation.
3Reliability
If trenches are formed to create isolation structures, then optical and electrical isolation is achieved, but molecular bonds in the substrate are disrupted creating structural defects
Solution Approach 1:
The trench depth parameter is optimized to extend through the substrate thickness but not excessively beyond, balancing isolation effectiveness with minimal bond disruption. By precisely controlling the trench depth parameter to match the substrate thickness, the design achieves effective isolation while minimizing the volume of disrupted molecular bonds and associated structural defects.
4Device complexity
If additional circuit resources are incorporated within a single CIS IC device to reduce PCB footprint, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The deep trench isolation structure serves multiple functions simultaneously: it provides optical isolation to prevent light crosstalk, electrical isolation to prevent signal interference, and mechanical structuring for subsequent circuit fabrication. This multi-functionality reduces the need for separate isolation structures and simplifies the overall manufacturing process despite high device integration.
Data Source
AI summary
Some embodiments relate to an integrated circuit device having an IC layer including a plurality of pixel cell groups. Each pixel cell group includes a plurality of pixel cells arranged in a 2-by-2 configuration. Each pixel cell includes a photodetector in a substrate, and a transfer transistor electrically coupled to the photodetector and configured to transfer electrical charge collected at the photodetector across a first surface of the substrate. The IC layer further includes at least one dielectric structure extending from the first surface to a second surface of the substrate and separating each pixel cell from neighboring pixel cells. The dielectric structure includes a first gap disposed at a common corner of the pixel cells. A conductive structure is electrically connected to at least one of the photodetector or the transfer transistor of each of the pixel cells and is disposed in the first gap over the first surface.