Static CMOS Full Adder Layout With Lower Transistor Count
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Solution Overview
Problem
Conventional CMOS-based mirror full adders in SoCs have high transistor counts, leading to increased area and power consumption, which is detrimental for AI/ML applications, and result in reduced performance due to high input capacitance and delay in sum and carry output arcs.
Innovation Solution
A CMOS-based Full Adder circuit design that reduces the number of transistors by optimizing the sum and carry output generation circuits using exclusive-NOR, OR-AND-INVERT, and NAND gates, limiting each input pin to fewer transistors, thereby reducing input capacitance and overall delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional CMOS-based mirror full adder is used, then the full adder can be implemented with standard circuit topology, but the transistor count increases to 28, leading to increased area and power consumption
Solution Approach 1:
The patent extracts and removes redundant transistors from the conventional full adder circuit. Specifically, it eliminates unnecessary transistor instances in the sum and carry generation logic, reducing the total count from 28 to 24 transistors while preserving the essential full adder functionality. This extraction of redundant elements directly addresses the contradiction by decreasing quantity without compromising manufacturability.
Solution Approach 2:
The patent merges certain logic functions into more efficient gate structures. By combining multiple transistor functions into optimized gate configurations, the design achieves the same logical operations with fewer transistors, thereby reducing area and power consumption while maintaining ease of manufacture through standardized gate implementations.
2Adaptability or versatility
If input pins A and B are connected to 8 MOS transistors each and CI to 6 MOS transistors, then the full adder can handle all input combinations, but the input capacitance increases and performance factor is reduced
Solution Approach 1:
The patent extracts and removes redundant transistor connections from the input pins. By eliminating unnecessary transistor instances that were previously connected to inputs A, B, and CI, the design reduces the number of transistor gates each input must drive, thereby reducing input capacitance and improving signal transition speed while maintaining full input handling capability.
3Reliability
If 3 MOS stacking of PMOS and NMOS transistors is used in the sum generation path, then the circuit can generate correct sum output, but the delay in sum and carry output arcs increases
Solution Approach 1:
The patent segments the sum generation path to avoid deep transistor stacking. By dividing the logic into shallower stages with parallel pathways, the design reduces the critical path delay while maintaining correct sum output generation. This segmentation breaks the 3-MOS-stack bottleneck into multiple shorter stages.
Solution Approach 2:
The patent introduces parallel logic pathways that operate in different dimensional spaces of the circuit. By creating alternative signal paths with different transistor stacking configurations, the design provides multiple routes for signal propagation, reducing the effective delay through dimensional diversification of the logic paths.
4Area of stationary object
If carry propagation circuit and carry generation circuit are combined in a single stage, then the circuit area is reduced, but the carry output delay increases
Solution Approach 1:
The patent segments the carry output generation into distinct propagation and generation stages. By separating these functions into different logical stages with controlled timing, the design reduces carry output delay while maintaining compact area through shared transistor resources between stages. This segmentation allows optimized timing without excessive area expansion.
Data Source
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AI summary
Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or- and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.