CMOS Gate Stack Planarization via Preliminary Dielectric Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of advanced integrated circuits, such as CMOS transistors, faces challenges due to the presence of 'bumps' caused by uneven surface planarity during the manufacturing process, leading to time-consuming and expensive chemical mechanical polishing (CMP) operations and potential variations in gate electrode structures, which can result in degraded performance.
Innovation Solution
A novel process flow involving the formation of gate stacks with three layers of hard mask material, sidewall spacers, a polish stop layer, and controlled etching and CMP processes to reduce substrate recessing and eliminate bumps, ensuring planarity and consistent gate structure height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMOS fabrication processes are used, then transistors are formed on the substrate, but bumps are created causing uneven surface planarity
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer of dielectric material over the substrate before forming the gate electrode structures. This pre-planarization step prevents bumps from creating surface irregularities that would otherwise require subsequent CMP operations, thereby maintaining surface planarity throughout the fabrication process.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary element between the substrate and the gate electrode structures. This intermediate dielectric layer absorbs and compensates for surface irregularities and bumps, providing a flat upper surface for subsequent processing without requiring extensive CMP operations.
2Manufacturing precision
If CMP operations are performed to remove bumps, then surface planarity is improved, but the process becomes time-consuming and expensive
Solution Approach 1:
The patent performs planarization in advance by depositing a planarization layer before forming the gate structures, eliminating the need for time-consuming CMP operations later in the process. This preliminary planarization step maintains surface flatness throughout subsequent fabrication steps.
Solution Approach 2:
The patent replaces the mechanical CMP process with a deposition-based planarization approach. Instead of mechanically removing material through CMP, the patent deposits a dielectric planarization layer that automatically provides a flat surface, substituting a faster, less expensive process for the traditional mechanical removal method.
3Manufacturing precision
If CMP operations are performed to remove bumps, then surface planarity is improved, but variations in gate electrode structures occur leading to degraded performance
Solution Approach 1:
The patent forms the planarization layer before creating gate electrode structures, ensuring that all subsequent layers are deposited on a uniformly flat surface. This preliminary planarization prevents variations in gate electrode thickness and dimensions that would otherwise result from CMP-induced surface irregularities.
Solution Approach 2:
The planarization layer serves as an intermediary that isolates the gate electrode structures from underlying bumps and surface irregularities. This intermediate dielectric layer ensures uniform gate structure formation by providing a consistent, flat deposition surface, thereby improving gate structure uniformity and device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for extensive CMP operations, minimizes substrate recessing, and enhances the uniformity of gate structures, thereby improving the performance and reliability of integrated circuit devices by maintaining surface planarity and reducing variations in gate electrode thickness.
Implementation Method 1
performing at least one chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer
Data Source
AI summary
One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.