Semiconductor/Solid-State Device Manufacturing TRIZ Cases

A patterned metal catalyst stamp transfers etching agents to a substrate through direct contact pressure.

Helium and hydrogen ion implantation creates a modified film that enhances etching selectivity, reducing lateral attack on non-etched layers.

A semiconductor patterning method uses sequential hard mask and strip layers with alternating materials to form high-resolution features through self-aligned cutting.

A buffer layer pattern controls oxidation to form a uniform gate insulating film within silicon carbide vertical trench MOSFETs.

Laser forms a peel-off layer in SiC ingots while ultrasonic waves break the modified region for wafer separation.

Segmented gate dielectric layers prevent leakage and extrusion paths in FinFETs, expanding the process window for sequential depositions.

A control unit dynamically reroutes substrates to available modules within a multi-module processing system.

Alternating plasma and non-plasma cycles suppresses particle generation while maintaining high film formation rates.

Segmented capping layers with defined thickness ratios minimize source drain loss during etching to improve manufacturing efficiency.

A compliant needle mechanism transfers unpackaged semiconductor dies directly to circuit substrates.

Offset trajectories from asymmetric supporting portions reduce depth interference between the transfer device and storage rack.

A chemical-mechanical polishing composition with colloidal silica and hydrogen peroxide polishes nickel-phosphorous substrates.

Epitaxial growth in sidewall recesses defines a uniform silicon alloy fin, preventing faceted growth and short channel effects.

A wurtzite III-nitride field effect transistor uses an undercoat layer to reduce contact resistance.

Combining pulsed plasma lamp and laser processing enables selective area treatment and large-area efficiency for semiconductor manufacturing.

Drive-in annealing diffuses boron into silicon germanium fins to overcome strain relaxation and achieve conformal channel mobility.

A laser beam directs heat onto ceramic structural bodies to heal surface microcracks and increase Vickers hardness.

Alternating precursor and amine-based catalytic ozone cycles form oxide films while reducing catalytic gas consumption and process complexity.

A substrate storing method manages unprocessed and processed wafers between containers using a transferring module.

A semiconductor light emitting device uses a metal separation area between the side electrode and insulator film to reflect emitted light.

Hydrogen annealing removes native oxides and silicon nitrides from silicon substrates, enabling high-quality SiGe crystal growth with improved crystallinity.

Gas charging portion injects inert gas into wafer stacking portion to displace residual moisture and prevent contamination.

Mask layers prevent dopant diffusion during thermal oxidation, isolating split gates in power MOSFETs to stop leakage.

Gallium nitride merged P-i-N Schottky diodes use regrowth and etch back processes to lower leakage current while maintaining low turn-on voltage.

Self-aligned implantation creates uniform compensation layers parallel to trench sidewalls, resolving charge balance precision against manufacturing complexity.

Placing source metal below and drain metal above the device layer reduces parasitic capacitance by eliminating pass-thru conductors in the drain interconnect.

A double-layered electrode structure enhances carrier transfer efficiency in solar cells.

A substrate processing boat uses vertical rod holders and susceptor support tips to position wafers for uniform film deposition.

Aminosilane-based gas adsorption enables selective silicon-based insulating film growth on mixed underlayers.

In-situ lateral etching trims silicon germanium source/drain width, preventing electrical shorts in narrow fin pitch areas while maintaining device performance.

Segmented evaluation modifies mask design features to suppress rippling caused by high spatial frequencies in low k1 photolithography.

A through-type furnace uses a movable clamp along a longitudinal slit to transport substrates while maintaining a protective gas environment.

Segmenting the etch into distinct plasma steps controls hard mask profiles to prevent liner pinch-off and reduce defects at small feature sizes.

Segmenting the planar gate and adding a high-concentration JFET diffusion region stabilizes threshold voltage while minimizing on-resistance.

Filler layer establishes uniform surface before second patterning step, reducing critical dimension bias between double exposure cycles.

Segmenting the gate dielectric into an oxidized capping layer and a thermal CVD oxide preserves SiGe epitaxial integrity while improving TDDB reliability.

Electrolyte solution containing aromatic amines and electrochemically inert cations improves copper nucleation density on metal substrates.

A thermally sprayed insulating film incorporates a buffering layer to prevent contact damage from thermal expansion stress during high temperature processing.

Segmented eSiGe source-drain structures confine silicide depth while maintaining active boron concentration and channel strain.

A power diode termination region uses variable doping pockets to reduce peak electric fields.

Exciting oxygen gas with a fluorine mixture enables selective silicon nitride etching while preventing damage to adjacent polysilicon and oxide layers.

Oxygen and boron trichloride plasma steps thin the AlGaN layer uniformly, resolving threshold voltage instability in normally-off devices.

Variable thickness inorganic layers enable selective etch-back to define array features while protecting periphery masks, reducing lithography steps.

A photosensitive polyimide composition combines specific resin units with thermal curing agents to create a robust photoresist film.

Bromine and oxygen plasma etches anti-reflective coatings and nitride layers with high oxide selectivity, eliminating polymeric byproduct deposition.

Gas injection into the gap between plate and wafer prevents vacuum formation that causes substrate warping or cracking.

A CMOS gate stack structure uses a preliminary dielectric layer to establish surface planarity before electrode formation.

Isolation barriers segment silicon carbide substrates into independent device islands.

Selective hard mask removal enables local interconnect routing over gates without shorts, resolving area penalties at 15 nm nodes.