Vertically Opposed Source and Drain Metal Interconnects
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Solution Overview
Problem
MOSFET-based integrated circuit fabrication processes face issues with parasitic capacitance due to overlaid source and drain metal interconnects, which degrade transistor performance.
Innovation Solution
The configuration of metal interconnects is modified by placing the drain metal interconnect above the transistor device layer and the source metal interconnect below it, reducing parasitic capacitance and improving RC performance by minimizing the need for pass-thru conductors and allowing for wider interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source and drain metal interconnects are overlaid on the same side of the transistor, then the interconnect structure is simple and easy to manufacture, but parasitic capacitance increases degrading transistor performance
Solution Approach 1:
The patent moves the source and drain metal interconnects from a two-dimensional overlaid configuration to a three-dimensional vertically opposed configuration, with the drain interconnect above the transistor device layer and the source interconnect below it. This dimensional change separates the interconnects in the vertical dimension, reducing parasitic capacitance while maintaining manufacturing feasibility through standard deposition processes.
Solution Approach 2:
The transistor device layer itself acts as an intermediary element that physically separates the source and drain metal interconnects. By placing the drain interconnect above the device layer and the source interconnect below it, the device layer serves as a natural barrier that reduces capacitive coupling between the interconnects, eliminating the need for additional shielding structures.
2Reliability
If pass-thru conductors are used in the drain metal interconnect layer to access upper conductors, then connectivity is maintained, but parasitic capacitance increases and interconnect width is reduced
Solution Approach 1:
The patent extracts the source interconnect from the drain metal interconnect layer and places it in a separate layer below the transistor device layer. This separation eliminates the need for pass-thru conductors in the drain metal interconnect layer, removing the source of parasitic capacitance while maintaining all necessary electrical connectivity through direct connections to the source and drain regions.
Solution Approach 2:
By moving the source interconnect to a lower layer in the vertical dimension, the patent eliminates the need for lateral pass-thru conductors that would be required in a planar configuration. This vertical separation allows the drain metal interconnect layer to have wider conductors without requiring narrow pass-thru features, reducing parasitic capacitance while maintaining connectivity.
3Area of stationary object
If interconnects are placed closer together to reduce area, then space is saved, but parasitic capacitance increases degrading RC performance
Solution Approach 1:
The patent utilizes the vertical dimension to separate source and drain interconnects into different layers, with the drain interconnect above the transistor device layer and the source interconnect below it. This vertical separation allows for wider interconnects with larger spacing in the lateral dimension without increasing parasitic capacitance, as the capacitive coupling is reduced by the vertical distance and the transistor device layer barrier.
Data Source
AI summary
Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.