SiGe Source/Drain Lateral Etching for FinFET Isolation
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Solution Overview
Problem
In high-density areas of semiconductor chips with narrow fin pitch, silicon germanium epitaxial layers on source/drain terminals of fin field effect transistors (FINFETs) can electrically short, leading to performance degradation and wafer yield loss.
Innovation Solution
An in-situ lateral etching process is employed to trim the sides of epitaxially grown silicon germanium source/drain regions, reducing their width while maintaining height and adjusting dopant concentrations to prevent electrical shorts without compromising FINFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon germanium epitaxial layers are grown on source/drain terminals in high density areas with narrow fin pitch, then device density and integration are improved, but electrical shorts between neighboring FINFETs occur leading to performance degradation and wafer yield loss
Solution Approach 1:
The source/drain regions are segmented into multiple epitaxial layers with different compositions and properties. The first SiGe layer provides initial coverage, the second SiGe layer with higher Ge content provides stress engineering and electrical isolation, and the Si cap layer provides final protection and isolation. This segmentation allows each layer to contribute specifically to preventing electrical shorts while maintaining device density.
Solution Approach 2:
Different regions of the source/drain structure are given different local qualities through selective epitaxial growth. The SiGe layers have different Ge atomic percentages (first layer: lower Ge content, second layer: higher Ge content of 40-80%) to provide different functions. The lateral etching selectively removes material from specific areas to create regions with different electrical properties, ensuring proper isolation between neighboring FINFETs while maintaining conductivity where needed.
2Reliability
If lateral etching is performed to reduce source/drain region width and prevent electrical shorts, then electrical isolation between neighboring fins is improved, but FINFET performance may be compromised
Solution Approach 1:
The invention changes multiple parameters to resolve the contradiction: (1) Ge atomic percentage is varied between layers (first SiGe layer has lower Ge content, second SiGe layer has 40-80% Ge content) to provide different electrical and mechanical properties; (2) layer thicknesses are optimized (first SiGe layer: 5-20nm, second SiGe layer: 20-50nm, Si cap layer: 5-20nm); (3) dopant concentrations are adjusted in different layers to maintain electrical performance; (4) lateral etching depth and duration are controlled to achieve the desired width reduction while preserving essential device function.
Solution Approach 2:
The source/drain structure uses composite materials consisting of multiple SiGe layers with different Ge compositions combined with a Si cap layer. This composite structure provides both the electrical isolation needed to prevent shorts (through the higher Ge content second layer and Si cap) and the electrical performance needed for device operation (through the lower Ge content first layer and controlled doping). The lateral etching further refines this composite structure to achieve optimal isolation while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively minimizes electrical shorts between neighboring FINFETs, ensuring optimal electrical properties and maintaining device performance by selectively etching the SiGe S/D regions along the (110) plane, thereby enhancing wafer yield and preventing performance degradation.
Implementation Method 1
silicon germanium epitaxial layers formed on source/drain terminals
Implementation Method 2
An in-situ lateral etching process is employed to trim the sides of epitaxially grown silicon germanium source/drain regions
Data Source
AI summary
The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.