Gate Dielectric Segmentation for SiGe Epitaxial Integrity
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Solution Overview
Problem
The formation of a reliable gate dielectric layer in semiconductor devices, particularly in those combining logic and CPU with DRAM or SRAM, is challenging due to the need for precise temperature control to avoid degrading the epitaxial layer characteristics, such as silicon-germanium (Si-Ge), which can lead to poor Time Dependent Dielectric Breakdown (TDDB) characteristics and reliability issues.
Innovation Solution
A method involving the formation of an epitaxial layer on a semiconductor substrate, followed by a capping layer that is oxidized in an oxygen atmosphere at temperatures between 600° C. and 800° C. to create a first gate dielectric layer, with a subsequent thermal chemical vapor deposition (CVD) oxide layer formation to create a second gate dielectric layer, ensuring the capping layer's thickness is about half of the total gate dielectric layer thickness, thereby maintaining the epitaxial layer's characteristics and improving TDDB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer is formed at high temperature to ensure good dielectric properties, then the TDDB characteristics are improved, but the epitaxial layer characteristics are degraded due to Ge agglomeration
Solution Approach 1:
The gate dielectric layer is divided into two distinct layers: a first gate dielectric layer formed by oxidizing the capping layer at lower temperature (600-800°C), and a second gate dielectric layer formed by thermal CVD at higher temperature. This segmentation allows each layer to be optimized for different functions - the first layer protects the epitaxial layer from high-temperature damage while the second layer provides the necessary dielectric properties for good TDDB characteristics.
Solution Approach 2:
The first gate dielectric layer acts as an intermediary protective layer between the epitaxial layer and the high-temperature processing environment. It prevents direct exposure of the epitaxial layer to high temperatures that would cause Ge agglomeration, while still allowing the formation of the second gate dielectric layer with proper dielectric properties.
2Ease of manufacture
If a single gate dielectric layer is formed to simplify the process, then the manufacturing complexity is reduced, but the reliability is compromised due to inability to protect epitaxial layer from high temperature damage
Solution Approach 1:
The gate dielectric layer is divided into two distinct layers: a first gate dielectric layer formed by oxidizing the capping layer at lower temperature (600-800°C), and a second gate dielectric layer formed by thermal CVD at higher temperature. This segmentation allows each layer to be optimized for different functions - the first layer protects the epitaxial layer from high-temperature damage while the second layer provides the necessary dielectric properties for good TDDB characteristics.
Solution Approach 2:
The first gate dielectric layer is formed in advance before the high-temperature thermal CVD process. This preliminary action creates a protective barrier that prevents the epitaxial layer from being exposed to damaging high temperatures during subsequent processing steps.
3Stability of the object's composition
If the capping layer thickness is increased to provide better protection, then the epitaxial layer integrity is maintained, but the total gate dielectric layer thickness becomes excessive
Solution Approach 1:
The capping layer thickness is set to approximately half of the total gate dielectric layer thickness, which is sufficient to provide the necessary protection during oxidation and serve as the first gate dielectric layer, while avoiding excessive thickness that would compromise device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with superior TDDB characteristics and reliability, as the gate dielectric layers are formed at optimal temperatures that prevent Ge agglomeration and maintain the epitaxial layer's integrity, leading to improved mobility and charge leakage characteristics without degrading the underlying layer's properties.
Implementation Method 1
oxidizing the capping layer in an atmosphere containing oxygen to form a first gate dielectric layer
Implementation Method 2
forming the second gate dielectric layer comprises performing a thermal chemical vapor deposition (CVD) oxide layer formation method
Data Source
AI summary
A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.